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31. 发明申请

US20090289291A1 SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER 失效
标题翻译： SOI深层电容器采用不合格的内部间隔器
公开(公告)号：US20090289291A1
公开(公告)日：2009-11-26
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

32. 发明授权

US07550359B1 Methods involving silicon-on-insulator trench memory with implanted plate 有权
标题翻译：涉及具有植入板的绝缘体上硅沟槽存储器的方法
公开(公告)号：US07550359B1
公开(公告)日：2009-06-23
申请号：US12116626
申请日：2008-05-07
申请人： Kangguo Cheng , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： A method for fabricating silicon-on-insulator (SOI) trench memory includes forming a trench on a substrate, wherein a buried oxide layer is disposed on the substrate, a SOI layer is disposed on the buried oxide layer, and a hardmask layer is disposed on the SOI layer, implanting ions into the substrate and the SOI layer on a first opposing side of the trench and a second opposing side the trench to partially form a capacitor, depositing a node dielectric in the trench, filling the trench with a first polysilicon, removing a portion of the first polysilicon from the trench, removing an exposed portion of the node dielectric, filling the trench with a second polysilicon, masking to define an active region on the hardmask layer, forming shallow trench isolation (STI) such that the STI contacts a portion of the buried oxide layer, removing the hardmask layer, and forming a transistor.
摘要翻译：一种用于制造绝缘体上硅（SOI）沟槽存储器的方法，包括在衬底上形成沟槽，其中掩埋氧化物层设置在衬底上，SOI层设置在掩埋氧化物层上，并且设置硬掩模层在所述SOI层上，将离子注入到所述衬底中并且在所述沟槽的第一相对侧上的所述SOI层和所述沟槽的第二相对侧，以部分地形成电容器，在所述沟槽中沉积节点电介质，用第一多晶硅填充所述沟槽从所述沟槽去除所述第一多晶硅的一部分，去除所述节点电介质的暴露部分，用第二多晶硅填充所述沟槽，以掩蔽以限定所述硬掩模层上的有源区域，形成浅沟槽隔离（STI），使得 STI接触掩埋氧化物层的一部分，去除硬掩模层，并形成晶体管。

33. 发明授权

US06297127B1 Self-aligned deep trench isolation to shallow trench isolation 失效
标题翻译：自对准深沟槽隔离到浅沟槽隔离
公开(公告)号：US06297127B1
公开(公告)日：2001-10-02
申请号：US09599699
申请日：2000-06-22
申请人： Bomy A. Chen , Liang-Kai Han , Robert Hannon , Jay G. Harrington , Herbert L. Ho , Hsing-Jen Wann
发明人： Bomy A. Chen , Liang-Kai Han , Robert Hannon , Jay G. Harrington , Herbert L. Ho , Hsing-Jen Wann
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.
摘要翻译：浅沟槽隔离与在浅沟槽的角部处与浅沟槽自对准的可选深沟槽组合，并且具有深沟槽宽度，其由沉积在浅层的内部中的临时侧壁的厚度控制并且受到深沟槽填充物的侧壁沉积厚度的限制。

34. 发明申请

US20130249052A1 CREATING DEEP TRENCHES ON UNDERLYING SUBSTRATE 有权
标题翻译：在基础上创建深度倾斜
公开(公告)号：US20130249052A1
公开(公告)日：2013-09-26
申请号：US13428004
申请日：2012-03-23
申请人： Jennifer E. Appleyard , John E. Barth, JR. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
发明人： Jennifer E. Appleyard , John E. Barth, JR. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L21/76898 , H01L27/0805 , H01L28/91 , H01L29/945
摘要： A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
摘要翻译：公开了半导体结构及其制造方法。在一个实施例中，该结构包括在衬底中具有掩埋板或板的第一衬底。每个掩埋板包括至少一个掩埋板触点和围绕至少一个掩埋板触点设置的多个深沟槽电容器。第一氧化物层设置在第一衬底上。可以访问第一衬底中的深沟槽电容器和掩埋板触点，以用于各种存储器和去耦应用。

35. 发明申请

US20120083092A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120083092A1
公开(公告)日：2012-04-05
申请号：US13323033
申请日：2011-12-12
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.
摘要翻译：提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层的沟槽。在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

36. 发明授权

US08110464B2 SOI protection for buried plate implant and DT bottle ETCH 失效
标题翻译：掩埋板植入物和DT瓶ETCH的SOI保护
公开(公告)号：US08110464B2
公开(公告)日：2012-02-07
申请号：US12048291
申请日：2008-03-14
申请人： Thomas W. Dyer , Herbert L. Ho , Ravi M. Todi
发明人： Thomas W. Dyer , Herbert L. Ho , Ravi M. Todi
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial trench may stop on BOX underlying the SOI. The band of oxide may also protect the SOI during buried plate implant or gas phase doping.
摘要翻译：在深沟槽蚀刻之前，SOI层具有穿过其延伸的初始沟槽。执行氧化步骤，例如热氧化，以在SOI层的内周上形成氧化带，以在随后的用于形成深沟槽的RIE步骤中保护它。初始沟槽可能停在SOI上的BOX上。在掩埋板植入或气相掺杂期间，氧化物带也可以保护SOI。

37. 发明授权

US07750388B2 Trench metal-insulator metal (MIM) capacitors 失效
标题翻译：沟槽金属绝缘体金属（MIM）电容器
公开(公告)号：US07750388B2
公开(公告)日：2010-07-06
申请号：US11961076
申请日：2007-12-20
申请人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
发明人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
IPC分类号： H01L31/062 , H01L29/94 , G06F9/45
CPC分类号： H01L28/91 , H01L27/10861
摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.
摘要翻译：本发明涉及一种包含沟槽金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）的半导体器件，以及包括体现在机器可读介质中的半导体器件的设计结构。沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。沟槽MIM电容器通过金属带连接到FET。本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

38. 发明申请

US20090230508A1 SOI PROTECTION FOR BURIED PLATE IMPLANT AND DT BOTTLE ETCH 失效
标题翻译：刨花板植入物和DT瓶盖的SOI保护
公开(公告)号：US20090230508A1
公开(公告)日：2009-09-17
申请号：US12048291
申请日：2008-03-14
申请人： Thomas W. Dyer , Herbert L. Ho , Ravi M. Todi
发明人： Thomas W. Dyer , Herbert L. Ho , Ravi M. Todi
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L21/3086 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial trench may stop on BOX underlying the SOI. The band of oxide may also protect the SOI during buried plate implant or gas phase doping.
摘要翻译：在深沟槽蚀刻之前，SOI层具有穿过其延伸的初始沟槽。执行氧化步骤，例如热氧化，以在SOI层的内周上形成氧化带，以在随后的用于形成深沟槽的RIE步骤中保护它。初始沟槽可能停在SOI上的BOX上。在掩埋板植入或气相掺杂期间，氧化物带也可以保护SOI。

39. 发明申请

US20090095998A1 DEEP TRENCH CAPACITOR AND METHOD 有权
标题翻译：深层电容电容器和方法
公开(公告)号：US20090095998A1
公开(公告)日：2009-04-16
申请号：US11872970
申请日：2007-10-16
申请人： Herbert L. Ho , Steven M. Shank
发明人： Herbert L. Ho , Steven M. Shank
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors.
摘要翻译：这里公开了深沟槽电容器结构的实施例以及形成结构的方法，该结构包括使用相邻的深沟槽同时形成的埋入电容器板接触。该配置消除了对附加光刻处理的需要，从而优化处理窗口。该配置还消除了通过N掺杂扩散区连接器形成深沟槽电容器的需要，从而当将深沟槽电容器连接到另一集成电路结构（例如，存储器单元或去耦电容器阵列）。此外，本文公开的是另一集成电路结构和方法，更具体地，存储器单元（例如，静态随机存取存储器（SRAM）单元））的实施例）以及形成包含这些深度中的一个或多个的存储器单元的方法沟槽电容器，以减少或消除软错误。

40. 发明申请

US20090079030A1 Forming SOI Trench Memory with Single-Sided Buried Strap 失效
标题翻译：形成具有单面埋地带的SOI沟槽存储器
公开(公告)号：US20090079030A1
公开(公告)日：2009-03-26
申请号：US12169727
申请日：2008-07-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/02 , H01L29/92
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

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