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1. 发明授权

US07951666B2 Deep trench capacitor and method 有权
标题翻译：深沟槽电容器及方法
公开(公告)号：US07951666B2
公开(公告)日：2011-05-31
申请号：US11872970
申请日：2007-10-16
申请人： Herbert L. Ho , Steven M. Shank
发明人： Herbert L. Ho , Steven M. Shank
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L29/66181
摘要： Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors.
摘要翻译：这里公开了深沟槽电容器结构的实施例以及形成结构的方法，该结构包括使用相邻的深沟槽同时形成的埋入电容器板接触。该配置消除了对附加光刻处理的需要，从而优化处理窗口。该配置还消除了通过N掺杂扩散区连接器形成深沟槽电容器的需要，从而当将深沟槽电容器连接到另一集成电路结构（例如，存储器单元或去耦电容器阵列）。此外，本文公开的是另一集成电路结构和方法，更具体地，存储器单元（例如，静态随机存取存储器（SRAM）单元））的实施例）以及形成包含这些深度中的一个或多个的存储器单元的方法沟槽电容器，以减少或消除软错误。

2. 发明申请

US20090095998A1 DEEP TRENCH CAPACITOR AND METHOD 有权
标题翻译：深层电容电容器和方法
公开(公告)号：US20090095998A1
公开(公告)日：2009-04-16
申请号：US11872970
申请日：2007-10-16
申请人： Herbert L. Ho , Steven M. Shank
发明人： Herbert L. Ho , Steven M. Shank
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： Disclosed herein are embodiments of a deep trench capacitor structure and a method of forming the structure that incorporates a buried capacitor plate contact that is simultaneously formed using an adjacent deep trench. This configuration eliminates the need for additional photolithographic processing, thereby, optimizing process windows. This configuration further eliminates the need to form the deep trench capacitor through an N-doped diffusion region connector and, thereby, allows for greater design flexibility when connecting the deep trench capacitor to another integrated circuit structure (e.g., a memory cell or decoupling capacitor array). Also, disclosed herein are embodiments of another integrated circuit structure and method, and more specifically, a memory cell (e.g., a static random access memory (SRAM) cell)) and method of forming the memory cell that incorporates one or more of these deep trench capacitors in order to minimize or eliminate soft errors.
摘要翻译：这里公开了深沟槽电容器结构的实施例以及形成结构的方法，该结构包括使用相邻的深沟槽同时形成的埋入电容器板接触。该配置消除了对附加光刻处理的需要，从而优化处理窗口。该配置还消除了通过N掺杂扩散区连接器形成深沟槽电容器的需要，从而当将深沟槽电容器连接到另一集成电路结构（例如，存储器单元或去耦电容器阵列）。此外，本文公开的是另一集成电路结构和方法，更具体地，存储器单元（例如，静态随机存取存储器（SRAM）单元））的实施例）以及形成包含这些深度中的一个或多个的存储器单元的方法沟槽电容器，以减少或消除软错误。

3. 发明授权

US08946045B2 Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI) 有权
标题翻译：具有深沟槽（DT）结构的金属绝缘体金属（MIM）电容器和绝缘体上硅（SOI）
公开(公告)号：US08946045B2
公开(公告)日：2015-02-03
申请号：US13457601
申请日：2012-04-27
申请人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/02
CPC分类号： H01L28/40 , H01L21/84 , H01L27/1203 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
摘要翻译：公开了形成金属 - 绝缘体 - 金属（MIM）沟槽电容器的结构。该结构包括具有金属层和至少一个电介质层的多层基底。沟槽被蚀刻到衬底中，穿过金属层。沟槽衬有与金属层接触的金属材料，金属层包括电容器的第一节点。电介质材料将沟槽中的金属材料排列。沟槽填充有导体。将金属材料排列的电介质材料将导体与金属层和衬套在沟槽上的金属材料分开。导体包括电容器的第二节点。

4. 发明授权

US08586444B2 Creating deep trenches on underlying substrate 有权
标题翻译：在底层基底上创造深沟
公开(公告)号：US08586444B2
公开(公告)日：2013-11-19
申请号：US13428004
申请日：2012-03-23
申请人： Jennifer E. Appleyard , John E. Barth, Jr. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
发明人： Jennifer E. Appleyard , John E. Barth, Jr. , John B. DeForge , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson , Andrew A. Turner
IPC分类号： H01L21/20
CPC分类号： H01L28/40 , H01L21/76898 , H01L27/0805 , H01L28/91 , H01L29/945
摘要： A semiconductor structure and method of fabricating the same are disclosed. In an embodiment, the structure includes a first substrate having a buried plate or plates in the substrate. Each buried plate includes at least one buried plate contact, and a plurality of deep trench capacitors disposed about the at least one buried plate contact. A first oxide layer is disposed over the first substrate. The deep trench capacitors and buried plate contacts in the first substrate may be accessed for use in a variety of memory and decoupling applications.
摘要翻译：公开了半导体结构及其制造方法。在一个实施例中，该结构包括在衬底中具有掩埋板或板的第一衬底。每个掩埋板包括至少一个掩埋板触点和围绕至少一个掩埋板触点设置的多个深沟槽电容器。第一氧化物层设置在第一衬底上。可以访问第一衬底中的深沟槽电容器和掩埋板触点，以用于各种存储器和去耦应用。

5. 发明授权

US08372721B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08372721B2
公开(公告)日：2013-02-12
申请号：US13343850
申请日：2012-01-05
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

6. 发明授权

US08198169B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

7. 发明授权

US08129797B2 Work function engineering for eDRAM MOSFETs 有权
标题翻译： eDRAM MOSFET的工作功能工程
公开(公告)号：US08129797B2
公开(公告)日：2012-03-06
申请号：US12141311
申请日：2008-06-18
申请人： Xiangdong Chen , Herbert L. Ho , Geng Wang
发明人： Xiangdong Chen , Herbert L. Ho , Geng Wang
IPC分类号： H01L27/088
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/10894 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.
摘要翻译：嵌入式DRAM MOSFET包括阵列NFET，其具有包括高K电介质层的栅极堆叠，在其上沉积第一金属氧化物层（CD1），然后沉积导电层（TiN），然后沉积多晶硅层（Poly）。具有与阵列NFET基本相同的栅极叠层的逻辑PFET，以及具有第三栅极堆叠的逻辑NFET，其包括高K电介质层，在其上沉积导电层（TiN），然后沉积多晶硅层（Poly）高K电介质层与导电层（TiN）之间的第一金属氧化物层（CD1）。因此，阵列NFET可以具有比逻辑NFET更高的栅极堆叠功函数，但是与逻辑PFET基本上相同的栅极堆叠功能。

8. 发明申请

US20100283093A1 Structure and Method to Form EDRAM on SOI Substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20100283093A1
公开(公告)日：2010-11-11
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

9. 发明授权

US07791124B2 SOI deep trench capacitor employing a non-conformal inner spacer 失效
标题翻译： SOI深沟槽电容器采用非保形内隔板
公开(公告)号：US07791124B2
公开(公告)日：2010-09-07
申请号：US12124186
申请日：2008-05-21
申请人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
发明人： Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1087 , H01L27/1203 , H01L29/66181
摘要： A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.
摘要翻译：用于SOI电容器的瓶形沟槽通过简单的处理顺序形成。在深沟槽的侧壁上形成具有可选的适形电介质扩散阻挡层的非保形介电层。采用各向同性蚀刻，从深沟槽的底部去除非共形电介质层，留下覆盖掩埋绝缘体层和顶部半导体层的侧壁的电介质间隔物。深沟槽的底部被膨胀以形成瓶形沟槽，并且在掩埋绝缘体层的下方形成埋入的电镀层。在形成掩埋带的过程中，电介质间隔物可以是凹陷的，以形成围绕内电极的上部的分级厚度的介质环。或者，可以在形成掩埋带之前去除电介质间隔物。

10. 发明授权

US07776706B2 Forming SOI trench memory with single-sided buried strap 失效
标题翻译：形成具有单面埋地带的SOI沟槽存储器
公开(公告)号：US07776706B2
公开(公告)日：2010-08-17
申请号：US12169727
申请日：2008-07-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
发明人： Kangguo Cheng , Ramachandra Divakaruni , Herbert L. Ho , Geng Wang
IPC分类号： H01L21/8234
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译：形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。

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