专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07750388B2 Trench metal-insulator metal (MIM) capacitors 失效
标题翻译：沟槽金属绝缘体金属（MIM）电容器
公开(公告)号：US07750388B2
公开(公告)日：2010-07-06
申请号：US11961076
申请日：2007-12-20
申请人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
发明人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
IPC分类号： H01L31/062 , H01L29/94 , G06F9/45
CPC分类号： H01L28/91 , H01L27/10861
摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.
摘要翻译：本发明涉及一种包含沟槽金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）的半导体器件，以及包括体现在机器可读介质中的半导体器件的设计结构。沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。沟槽MIM电容器通过金属带连接到FET。本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

2. 发明授权

US07388244B2 Trench metal-insulator-metal (MIM) capacitors and method of fabricating same 有权
标题翻译：沟槽金属 - 绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US07388244B2
公开(公告)日：2008-06-17
申请号：US11162776
申请日：2005-09-22
申请人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
发明人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L27/1203
摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.
摘要翻译：本发明涉及一种包含沟槽金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）的半导体器件。沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。沟槽MIM电容器通过金属带连接到FET。本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

3. 发明申请

US20090159948A1 TRENCH METAL-INSULATOR METAL (MIM) CAPACITORS 失效
标题翻译：金属绝缘子金属（MIM）电容器
公开(公告)号：US20090159948A1
公开(公告)日：2009-06-25
申请号：US11961076
申请日：2007-12-20
申请人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
发明人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10861
摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.
摘要翻译：本发明涉及一种包含沟槽金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）的半导体器件，以及包括体现在机器可读介质中的半导体器件的设计结构。沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。沟槽MIM电容器通过金属带连接到FET。本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

4. 发明授权

US07276751B2 Trench metal-insulator-metal (MIM) capacitors integrated with middle-of-line metal contacts, and method of fabricating same 有权
标题翻译：与中间线金属触点集成的沟槽金属 - 绝缘体金属（MIM）电容器及其制造方法
公开(公告)号：US07276751B2
公开(公告)日：2007-10-02
申请号：US11162413
申请日：2005-09-09
申请人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
发明人： Herbert L. Ho , Subramanian S. Iyer , Vidhya Ramachandran
IPC分类号： H01L29/76
CPC分类号： H01L27/10861 , H01L28/91 , H01L29/945
摘要： The present invention relates to a semiconductor device that contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region. The present invention also relates to a fabrication process, which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material.
摘要翻译：本发明涉及一种半导体器件，其包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选至少一个场效应晶体管（FET）。沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。本发明还涉及一种制造工艺，其将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。

5. 发明申请

US20100283093A1 Structure and Method to Form EDRAM on SOI Substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20100283093A1
公开(公告)日：2010-11-11
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/10 , H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

6. 发明申请

US20120171827A1 STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US20120171827A1
公开(公告)日：2012-07-05
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

7. 发明授权

US07193262B2 Low-cost deep trench decoupling capacitor device and process of manufacture 有权
标题翻译：低成本深沟槽去耦电容器件及其制造工艺
公开(公告)号：US07193262B2
公开(公告)日：2007-03-20
申请号：US10905094
申请日：2004-12-15
申请人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
发明人： Herbert L. Ho , John E. Barth, Jr. , Ramachandra Divakaruni , Wayne F. Ellis , Johnathan E. Faltermeier , Brent A. Anderson , Subramanian S. Iyer , Deok-Kee Kim , Randy W. Mann , Paul C. Parries
IPC分类号： H01L29/94 , H01L29/00
CPC分类号： H01L27/0805 , H01L29/66181 , H01L29/945
摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.
摘要翻译：一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

8. 发明授权

US08629017B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08629017B2
公开(公告)日：2014-01-14
申请号：US13417900
申请日：2012-03-12
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

9. 发明授权

US08188528B2 Structure and method to form EDRAM on SOI substrate 有权
标题翻译：在SOI衬底上形成EDRAM的结构和方法
公开(公告)号：US08188528B2
公开(公告)日：2012-05-29
申请号：US12437242
申请日：2009-05-07
申请人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
发明人： Chengwen Pei , Kangguo Cheng , Herbert L. Ho , Subramanian S. Iyer , Byeong Y. Kim , Geng Wang , Huilong Zhu
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10829 , H01L27/10861 , H01L29/945
摘要： A memory device is provided that in one embodiment includes a trench capacitor located in a semiconductor substrate including an outer electrode provided by the semiconductor substrate, an inner electrode provided by a conductive fill material, and a node dielectric layer located between the outer electrode and the inner electrode; and a semiconductor device positioned centrally over the trench capacitor. The semiconductor device includes a source region, a drain region, and a gate structure, in which the semiconductor device is formed on a semiconductor layer that is separated from the semiconductor substrate by a dielectric layer. A first contact is present extending from an upper surface of the semiconductor layer into electrical contact with the semiconductor substrate, and a second contact from the drain region of the semiconductor device in electrical contact to the conductive material within the at least one trench.
摘要翻译：提供了一种存储器件，其在一个实施例中包括位于半导体衬底中的沟槽电容器，该半导体衬底包括由半导体衬底提供的外部电极，由导电填充材料提供的内部电极，以及位于外部电极和内电极以及位于沟槽电容器上方的半导体器件。半导体器件包括源极区，漏极区和栅极结构，其中半导体器件形成在通过介电层与半导体衬底分离的半导体层上。存在从半导体层的上表面延伸到与半导体衬底电接触的第一接触，以及从半导体器件的漏极区域与至少一个沟槽内的导电材料电接触的第二接触。

10. 发明授权

US08946045B2 Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI) 有权
标题翻译：具有深沟槽（DT）结构的金属绝缘体金属（MIM）电容器和绝缘体上硅（SOI）
公开(公告)号：US08946045B2
公开(公告)日：2015-02-03
申请号：US13457601
申请日：2012-04-27
申请人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/02
CPC分类号： H01L28/40 , H01L21/84 , H01L27/1203 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.
摘要翻译：公开了形成金属 - 绝缘体 - 金属（MIM）沟槽电容器的结构。该结构包括具有金属层和至少一个电介质层的多层基底。沟槽被蚀刻到衬底中，穿过金属层。沟槽衬有与金属层接触的金属材料，金属层包括电容器的第一节点。电介质材料将沟槽中的金属材料排列。沟槽填充有导体。将金属材料排列的电介质材料将导体与金属层和衬套在沟槽上的金属材料分开。导体包括电容器的第二节点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式