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31. 发明授权

US07462547B2 Method of fabricating a bipolar transistor having reduced collector-base capacitance 失效
标题翻译：制造具有减小的集电极 - 基极电容的双极晶体管的方法
公开(公告)号：US07462547B2
公开(公告)日：2008-12-09
申请号：US11633380
申请日：2006-12-04
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
摘要翻译：提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。

32. 发明申请

US20050026382A1 METHOD AND STRUCTURE FOR IMPROVED TRENCH PROCESSING 失效
标题翻译：改进TRENCH加工的方法和结构
公开(公告)号：US20050026382A1
公开(公告)日：2005-02-03
申请号：US10604594
申请日：2003-08-01
申请人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
发明人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10864
摘要： A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a capacitor is formed in the trench below the sacrificial collar. An integrated circuit includes a deep trench structure formed in a single-crystal region of a semiconductor substrate including an upper trench portion, the upper trench portion having an opening of rectangular shape. A lower trench portion is formed below the upper trench portion. The lower portion may be widened to have a bottle shape. Alternatively, the upper trench portion may be widened relative to the lower trench portion.
摘要翻译：提供一种通过在衬底中形成沟槽来制造沟槽电容器的方法。然后加宽沟槽，并且在加宽的沟槽的侧壁上形成牺牲套环。然后将沟槽垂直加深以在牺牲套环的侧壁下方延伸。随后，在牺牲套环下方的沟槽中形成电容器。集成电路包括形成在包括上沟槽部分的半导体衬底的单晶区域中的深沟槽结构，上沟槽部分具有矩形形状的开口。下沟槽部分形成在上沟槽部分的下方。下部可以被加宽以具有瓶子形状。或者，上沟槽部分可以相对于下沟槽部分加宽。

33. 发明授权

US06449202B1 DRAM direct sensing scheme 失效
标题翻译： DRAM直接感测方案
公开(公告)号：US06449202B1
公开(公告)日：2002-09-10
申请号：US09929593
申请日：2001-08-14
申请人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
发明人： Hiroyuki Akatsu , Louis L. Hsu , Jeremy K. Stephens , Daniel W. Storaska
IPC分类号： G11C700
CPC分类号： G11C7/062 , G11C11/4091
摘要： A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line. When sensing a low data signal, the signal developed on the bitline causes subthreshold voltage leakage current through the pFET device to charge the gate of the nFET device which is floating to amplify the signal developed on the bitline to pull down the precharged data line. When sensing a high data signal, the pFET device and the nFET device remain inactivated, and the data line remains at its precharge high voltage. An nFET writeback device is coupled between the data line and the bitline which is switched on to begin a data writeback into the memory cell when the signal develops on the data line.
摘要翻译：一种直接感测电路和方法，用于在数据读取操作中在数据线上从连接到位线的存储器单元读取数据，并且将数据线开放位线检测而不使用参考位线信号。在数据读取操作之前，位线和数据线都被预充电到预充电电压，并且感测节点被预充电到地。 pFET器件的栅极耦合到从存储器单元在位线上产生的信号，以检测和放大其信号电平，并且其源极耦合到耦合到感测节点的电压源及其漏极，使得信号发展位线决定了pFET器件导通的程度。 nFET器件的栅极耦合到感测节点以检测和放大其信号电平，并且其漏极耦合到数据线。当感测到低数据信号时，在位线上产生的信号导致通过pFET器件的阈值电压漏电流，以对nFET器件的栅极进行充电，该nFET器件的栅极被浮置以放大在位线上产生的信号，以将预充电的数据线拉下来。当感测高数据信号时，pFET器件和nFET器件保持不激活，并且数据线保持在其预充电高电压。当在数据线上产生信号时，nFET写回装置耦合在数据线和打开的位线之间，以开始对存储器单元的数据写回。

34. 发明授权

US06333274B2 Method of manufacturing a semiconductor device including a seamless shallow trench isolation step 失效
标题翻译：制造包括无缝浅沟槽隔离步骤的半导体器件的方法
公开(公告)号：US06333274B2
公开(公告)日：2001-12-25
申请号：US09052152
申请日：1998-03-31
申请人： Hiroyuki Akatsu , Soichi Nadahara , Takashi Nakao , Seiko Yoshida
发明人： Hiroyuki Akatsu , Soichi Nadahara , Takashi Nakao , Seiko Yoshida
IPC分类号： H01L21302
CPC分类号： H01L21/76224 , H01L21/31111 , H01L21/31612 , H01L27/10861
摘要： A trench is formed. A first TEOS film is deposited in the trench. Thereafter, the first TEOS film is etched back by a wet etching method up to a planarized surface of a substrate. In this way, seams and a void generated during the first TEOS film deposition step are exposed. This is attained by performing the etching under the conditions that an etching rate for the TEOS film of the upper portion of the trench is larger than that for the TEOS film of the bottom portion of the trench. Thereafter, a second TEOS film is deposited in the trench.
摘要翻译：形成沟槽。第一个TEOS膜沉积在沟槽中。此后，通过湿蚀刻方法将第一TEOS膜回蚀刻到基板的平坦化表面。以这种方式，暴露在第一TEOS膜沉积步骤期间产生的接缝和空隙。这是通过在沟槽上部的TEOS膜的蚀刻速率大于沟槽底部的TEOS膜的蚀刻速率的条件下进行蚀刻而实现的。此后，第二TEOS膜沉积在沟槽中。

35. 发明授权

US06319794B1 Structure and method for producing low leakage isolation devices 失效
标题翻译：用于生产低泄漏隔离装置的结构和方法
公开(公告)号：US06319794B1
公开(公告)日：2001-11-20
申请号：US09172697
申请日：1998-10-14
申请人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
发明人： Hiroyuki Akatsu , Tze-Chiang Chen , Laertis Economikos , Herbert L. Ho , Richard Kleinhenz , Jack A. Mandelman , Wesley C. Natzle
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.
摘要翻译：一种用于半导体器件的浅沟槽隔离结构和用于在半导体衬底内制造浅沟槽隔离器件的方法。浅沟槽隔离结构是无凹槽的，并且包括未退火的介电材料作为沟槽填充材料。其结构与其形成的半导体表面的交叉点不含氮化硅，但是隔离结构可以包括位于沟槽内并凹陷在半导体表面下方的氮化硅衬垫。

36. 发明授权

US6060388A Conductors for microelectronic circuits and method of manufacture 失效
标题翻译：微电子电路用导体及制造方法
公开(公告)号：US6060388A
公开(公告)日：2000-05-09
申请号：US960208
申请日：1997-10-29
申请人： Hiroyuki Akatsu , Russell H. Arndt , Bradley P. Jones , George F. Ouimet
发明人： Hiroyuki Akatsu , Russell H. Arndt , Bradley P. Jones , George F. Ouimet
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01P3/06 , H01L21/4763
CPC分类号： H01L21/76877
摘要： An integrated circuit (IC) conductor and the process of making the conductor. The conductor may be a monofilament conductor, a clad conductor or a coaxial conductor. A trench is formed in a dielectric layer. An outer material layer is deposited on the dielectric layer and in the trench, thick enough that the outer material layer merges together in a seam over the trench forming a void under the seam. The outer material layer is dielectric for the monofilament conductor, a cladding material for the clad conductor and conducting material for the coaxial conductor. The void is filled with a conductor for a monofilament or clad conductors. An inner dielectric liner layer is formed on the walls of the void and a core conductor is formed on the liner layer for the coaxial conductor.
摘要翻译：一种集成电路（IC）导体和制造导体的过程。导体可以是单丝导体，包层导体或同轴导体。在电介质层中形成沟槽。外部材料层沉积在电介质层和沟槽中，其厚度足够使得外部材料层在沟槽上的接缝中合并在一起形成接缝下方的空隙。外部材料层是用于单丝导体的电介质，用于包层导体的包覆材料和用于同轴导体的导电材料。空隙填充有用于单丝或包层导体的导体。内部电介质衬层形成在空隙的壁上，芯导体形成在用于同轴导体的衬垫层上。

37. 发明授权

US5807439A Apparatus and method for improved washing and drying of semiconductor wafers 失效
公开(公告)号：US5807439A
公开(公告)日：1998-09-15
申请号：US939547
申请日：1997-09-29
申请人： Hiroyuki Akatsu , Ravikumar Ramachandran
发明人： Hiroyuki Akatsu , Ravikumar Ramachandran
IPC分类号： H01L21/304 , H01L21/00 , F26B7/00
CPC分类号： H01L21/67028 , H01L21/67023 , Y10S134/902
摘要： Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

38. 发明授权

US08396823B2 Automatic designing system, automatic designing method and automatic designing program for automatically designing architecture for system components 失效
标题翻译：自动设计系统，自动设计方法和自动设计系统组件结构的设计程序
公开(公告)号：US08396823B2
公开(公告)日：2013-03-12
申请号：US12825830
申请日：2010-06-29
申请人： Hiroyuki Akatsu , Hisashi Miyashita , Hiroaki Nakamura , Takashi Nerome
发明人： Hiroyuki Akatsu , Hisashi Miyashita , Hiroaki Nakamura , Takashi Nerome
IPC分类号： G06F17/00
CPC分类号： G06N5/025 , G06F17/5095
摘要： An automatic designing system includes: a rule storage unit storing sets of rewrite rules for rewriting variable nodes of a hierarchically structured graph in a design architecture for the system; a search unit sequentially determining variable nodes as application targets for the rewrite rules by searching the graph, including components in the design architecture for the system to be designed, using a search tree; a judgment unit judging whether the rewrite rule is applicable to the determined variable node; and a rule application unit replacing the determined variable node with a partial graph, including at least one of fixed and variable nodes, according to the rewrite rule, in response to a judgment that the rewrite rule is applicable. The search unit performs the searching until an undefined variable node no longer exists in the graph to be designed, and performs backtracking on condition that no variable node is found.
摘要翻译：自动设计系统包括：规则存储单元，用于存储用于重构用于系统的设计架构中用于重写分层结构化图形的可变节点的重写规则; 搜索单元使用搜索树通过搜索包括要设计的系统的设计架构中的组件的图来顺序地将变量节点确定为重写规则的应用目标; 判断单元判断所述重写规则是否适用于所确定的变量节点; 以及规则应用单元，响应于可重写规则的判断，根据重写规则，用包括固定节点和可变节点中的至少一个的部分图替换确定的变量节点。搜索单元执行搜索，直到要设计的图中不再存在未定义的变量节点，并且在没有找到变量节点的条件下执行回溯。

39. 发明授权

US06967136B2 Method and structure for improved trench processing 失效
标题翻译：改进沟槽加工的方法和结构
公开(公告)号：US06967136B2
公开(公告)日：2005-11-22
申请号：US10604594
申请日：2003-08-01
申请人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
发明人： Hiroyuki Akatsu , Kangguo Cheng , Kenneth Settlemyer
IPC分类号： H01L21/20 , H01L21/8242
CPC分类号： H01L27/1087 , H01L27/10864
摘要： A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a capacitor is formed in the trench below the sacrificial collar. An integrated circuit includes a deep trench structure formed in a single-crystal region of a semiconductor substrate including an upper trench portion, the upper trench portion having an opening of rectangular shape. A lower trench portion is formed below the upper trench portion. The lower portion may be widened to have a bottle shape. Alternatively, the upper trench portion may be widened relative to the lower trench portion.
摘要翻译：提供一种通过在衬底中形成沟槽来制造沟槽电容器的方法。然后加宽沟槽，并且在加宽的沟槽的侧壁上形成牺牲套环。然后将沟槽垂直加深以在牺牲套环的侧壁下方延伸。随后，在牺牲套环下方的沟槽中形成电容器。集成电路包括形成在包括上沟槽部分的半导体衬底的单晶区域中的深沟槽结构，上沟槽部分具有矩形形状的开口。下沟槽部分形成在上沟槽部分的下方。下部可以被加宽以具有瓶子形状。或者，上沟槽部分可以相对于下沟槽部分加宽。

40. 发明授权

US06887761B1 Vertical semiconductor devices 失效
标题翻译：垂直半导体器件
公开(公告)号：US06887761B1
公开(公告)日：2005-05-03
申请号：US10708647
申请日：2004-03-17
申请人： Hiroyuki Akatsu , Thomas W. Dyer , Ravikumar Ramachandran , Kenneth T. Settlemyer, Jr.
发明人： Hiroyuki Akatsu , Thomas W. Dyer , Ravikumar Ramachandran , Kenneth T. Settlemyer, Jr.
IPC分类号： H01L21/336 , H01L21/762 , H01L29/78 , H01I29/76
CPC分类号： H01L29/66666 , H01L21/2257 , H01L21/76224 , H01L29/7827
摘要： A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.
摘要翻译：一种用于增加垂直半导体器件的阈值电压的方法和结构。该方法包括在其半导体材料具有垂直于衬底表面的取向平面的衬底中形成深沟槽。然后，在深沟槽的深度周围形成垂直晶体管。接下来，形成两个浅沟槽隔离，使得它们在有源区域中夹住深沟槽，并且两个浅沟槽隔离区域经由垂直于取向平面的平面邻接有源区。然后，垂直晶体管的沟道区域暴露在深沟槽中的大气中，然后化学蚀刻到平行于取向平面的平面上。然后，在深沟槽的壁上形成栅极电介质层。最后，深沟槽充满多晶硅，形成垂直晶体管的栅极。

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