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1. 发明授权

US08187930B2 Structure and layout of a FET prime cell 有权
标题翻译： FET素电池的结构和布局
公开(公告)号：US08187930B2
公开(公告)日：2012-05-29
申请号：US11923686
申请日：2007-10-25
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L21/337
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

2. 发明授权

US07190046B2 Bipolar transistor having reduced collector-base capacitance 失效
标题翻译：双极晶体管具有降低的集电极 - 基极电容
公开(公告)号：US07190046B2
公开(公告)日：2007-03-13
申请号：US10708860
申请日：2004-03-29
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at least one of a dielectric region and a void disposed in an undercut underlying the intrinsic base layer. An emitter layer overlies the intrinsic base layer, and a raised extrinsic base layer overlies the intrinsic base layer.
摘要翻译：提供了用于形成双极晶体管的结构和方法。如所公开的，提供覆盖在集电极层上的本征基层。低电容区域横向设置在集电极层附近。低电容区域包括设置在本征基层下面的底切中的电介质区域和空穴中的至少一个。发射极层覆盖本征基极层，凸起的非本征基极层覆盖本征基极层。

3. 发明授权

US07217988B2 Bipolar transistor with isolation and direct contacts 有权
标题翻译：双极晶体管具有隔离和直接接触
公开(公告)号：US07217988B2
公开(公告)日：2007-05-15
申请号：US10709905
申请日：2004-06-04
申请人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
发明人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.
摘要翻译：双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。消除了常规的通孔和掩埋层以及它们的相关电阻。晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。该结构提供了改进的电性能，包括改进的f T，F max和驱动电流。

4. 发明授权

US07611953B2 Bipolar transistor with isolation and direct contacts 失效
标题翻译：双极晶体管具有隔离和直接接触
公开(公告)号：US07611953B2
公开(公告)日：2009-11-03
申请号：US11677776
申请日：2007-02-22
申请人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
发明人： David C. Ahlgren , Gregory G. Freeman , Francois Pagette , Christopher M. Schnabel , Anna W. Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.
摘要翻译：双极晶体管具有通过金属化直接接触基极 - 集电极结下方的集电极，以降低集电极电阻。消除了常规的通孔和掩埋层以及它们的相关电阻。晶体管非常隔离，几乎消除了良好的衬底电容和器件到器件的漏电流。该结构提供了改进的电气性能，包括改进的fT，Fmax和驱动电流。

5. 发明申请

US20090019691A1 MICRO-ELECTROMECHANICAL SUB-ASSEMBLY HAVING AN ON-CHIP TRANSFER MECHANISM 失效
标题翻译：具有片上传输机制的微电子组件
公开(公告)号：US20090019691A1
公开(公告)日：2009-01-22
申请号：US10597012
申请日：2004-01-15
申请人： Christopher M. Schnabel , Peter A. Smith , John E. Florkey , Richard P. Volant
发明人： Christopher M. Schnabel , Peter A. Smith , John E. Florkey , Richard P. Volant
IPC分类号： H05K3/30
CPC分类号： B81C3/002 , Y10T29/4913 , Y10T29/49133 , Y10T29/53178 , Y10T29/53183 , Y10T29/53187
摘要： Carriers (10) holding parts (50) for assembling complex MEMS devices are transported to a central assembly location. The parts are stacked in a pre-assigned order and later released from their carriers. Alternatively, they are positioned over the appropriate location and released so as to fall into position as needed. The assembly area (100) includes a cavity below the plane of the carriers such that the parts held within the carrier drop into the cavity. Heating elements are integrated into the cavity to assist in the release of the parts. The cavity is supplied with parts by one or more carriers which are move around by any number of MEMS drive systems (200, 250). The cavity and some of the MEMS assembled therein deliver with precision amounts of materials as required suitable for biomedical applications, or may be processed in-situ, as in an on-chip laboratory.
摘要翻译：用于组装复杂MEMS器件的载体（10）保持部件（50）被运输到中心组装位置。这些部件以预先分配的顺序堆叠，然后从其运营商释放。或者，它们被定位在适当的位置上并被释放以便根据需要落入位置。组装区域（100）包括在载体平面下方的空腔，使得保持在载体内的部分落入空腔内。加热元件集成到腔体中以帮助部件的释放。空腔由一个或多个载体提供，该载体通过任何数量的MEMS驱动系统（200,250）移动。组装在其中的腔和一些MEMS提供精确量的材料，适合于生物医学应用，或者可以像在片上实验室一样原位加工。

6. 发明授权

US08829572B2 Structure and layout of a FET prime cell 有权
标题翻译： FET素电池的结构和布局
公开(公告)号：US08829572B2
公开(公告)日：2014-09-09
申请号：US13398408
申请日：2012-02-16
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L29/66 , H01L27/088 , H01L21/70 , H01L23/552
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

7. 发明授权

US07462547B2 Method of fabricating a bipolar transistor having reduced collector-base capacitance 失效
标题翻译：制造具有减小的集电极 - 基极电容的双极晶体管的方法
公开(公告)号：US07462547B2
公开(公告)日：2008-12-09
申请号：US11633380
申请日：2006-12-04
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
摘要翻译：提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。

8. 发明申请

US20120146104A1 STRUCTURE AND LAYOUT OF A FET PRIME CELL 有权
标题翻译： FET母细胞的结构和布局
公开(公告)号：US20120146104A1
公开(公告)日：2012-06-14
申请号：US13398408
申请日：2012-02-16
申请人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
发明人： Basanth Jagannathan , John J. Pekarik , Christopher M. Schnabel
IPC分类号： H01L29/06
CPC分类号： H01L29/78 , H01L23/4824 , H01L29/1087
摘要： Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate.
摘要翻译：制造半导体器件的方法包括在衬底中形成源极和漏极，在源极和漏极之间的衬底上形成栅极，形成与源电接触的衬底接触，以及形成与源极的电接触，漏极和栅极以及基板。

9. 发明授权

US07814454B2 Selectable device options for characterizing semiconductor devices 有权
标题翻译：用于表征半导体器件的可选择的器件选项
公开(公告)号：US07814454B2
公开(公告)日：2010-10-12
申请号：US11770303
申请日：2007-06-28
申请人： Anthony I. Chou , James S. Dunn , Brian M. Dufrene , Christopher H. Lumbra , Shreesh Narasimha , Christopher S. Putnam , BethAnn Rainey , Christopher M. Schnabel
发明人： Anthony I. Chou , James S. Dunn , Brian M. Dufrene , Christopher H. Lumbra , Shreesh Narasimha , Christopher S. Putnam , BethAnn Rainey , Christopher M. Schnabel
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/14 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices in an integrated circuit technology, and includes: a system for designing a plurality of device options for a set of chip pads; a system for designing a pseudo wiring layout for each of the plurality of device options; a system for selecting one of the device options; a system for mapping the pseudo wiring layout for a selected device option to a predetermined design level; and a system for outputting a configured mask design at the predetermined design level having a wiring layout mapped for the selected device option.
摘要翻译：一种允许多个设备放置在焊盘之间的系统，方法和程序产品，使得后端（BEOL）掩模更改可用于选择不同的设备选项。公开了一种用于实现用于表征集成电路技术中的器件的测试现场的系统，并且包括：用于为一组芯片焊盘设计多个器件选项的系统; 用于为所述多个设备选项中的每一个设计伪布线布局的系统; 用于选择所述设备选项之一的系统; 用于将所选择的设备选项的伪布线布局映射到预定设计级的系统; 以及用于在具有针对所选择的设备选项映射的布线布局的预定设计级别处输出配置的掩模设计的系统。

10. 发明授权

US07735216B2 Micro-electromechanical sub-assembly having an on-chip transfer mechanism 失效
标题翻译：具有片上传送机构的微机电子组件
公开(公告)号：US07735216B2
公开(公告)日：2010-06-15
申请号：US10597012
申请日：2004-01-15
申请人： Christopher M. Schnabel , Peter A. Smith , John E. Florkey , Richard P. Volant
发明人： Christopher M. Schnabel , Peter A. Smith , John E. Florkey , Richard P. Volant
IPC分类号： B23P19/00 , H05K3/30
CPC分类号： B81C3/002 , Y10T29/4913 , Y10T29/49133 , Y10T29/53178 , Y10T29/53183 , Y10T29/53187
摘要： Carriers (10) holding parts (50) for assembling complex MEMS devices are transported to a central assembly location. The parts are stacked in a pre-assigned order and later released from their carriers. Alternatively, they are positioned over the appropriate location and released so as to fall into position as needed. The assembly area (100) includes a cavity below the plane of the carriers such that the parts held within the carrier drop into the cavity. Heating elements are integrated into the cavity to assist in the release of the parts. The cavity is supplied with parts by one or more carriers which are move around by any number of MEMS drive systems (200, 250). The cavity and some of the MEMS assembled therein deliver with precision amounts of materials as required suitable for biomedical applications, or may be processed in-situ, as in an on-chip laboratory.
摘要翻译：用于组装复杂MEMS器件的载体（10）保持部件（50）被运输到中心组装位置。这些部件以预先分配的顺序堆叠，然后从其运营商释放。或者，它们被定位在适当的位置上并被释放以便根据需要落入位置。组装区域（100）包括在载体平面下方的空腔，使得保持在载体内的部分落入空腔内。加热元件集成到腔体中以帮助部件的释放。空腔由一个或多个载体提供，该载体通过任何数量的MEMS驱动系统（200,250）移动。组装在其中的腔和一些MEMS提供精确量的材料，适合于生物医学应用，或者可以像在片上实验室一样原位加工。

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