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1. 发明授权

US6060388A Conductors for microelectronic circuits and method of manufacture 失效
标题翻译：微电子电路用导体及制造方法
公开(公告)号：US6060388A
公开(公告)日：2000-05-09
申请号：US960208
申请日：1997-10-29
申请人： Hiroyuki Akatsu , Russell H. Arndt , Bradley P. Jones , George F. Ouimet
发明人： Hiroyuki Akatsu , Russell H. Arndt , Bradley P. Jones , George F. Ouimet
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01P3/06 , H01L21/4763
CPC分类号： H01L21/76877
摘要： An integrated circuit (IC) conductor and the process of making the conductor. The conductor may be a monofilament conductor, a clad conductor or a coaxial conductor. A trench is formed in a dielectric layer. An outer material layer is deposited on the dielectric layer and in the trench, thick enough that the outer material layer merges together in a seam over the trench forming a void under the seam. The outer material layer is dielectric for the monofilament conductor, a cladding material for the clad conductor and conducting material for the coaxial conductor. The void is filled with a conductor for a monofilament or clad conductors. An inner dielectric liner layer is formed on the walls of the void and a core conductor is formed on the liner layer for the coaxial conductor.
摘要翻译：一种集成电路（IC）导体和制造导体的过程。导体可以是单丝导体，包层导体或同轴导体。在电介质层中形成沟槽。外部材料层沉积在电介质层和沟槽中，其厚度足够使得外部材料层在沟槽上的接缝中合并在一起形成接缝下方的空隙。外部材料层是用于单丝导体的电介质，用于包层导体的包覆材料和用于同轴导体的导电材料。空隙填充有用于单丝或包层导体的导体。内部电介质衬层形成在空隙的壁上，芯导体形成在用于同轴导体的衬垫层上。

2. 发明授权

US07129169B2 Method for controlling voiding and bridging in silicide formation 有权
标题翻译：控制硅化物形成中孔隙和桥接的方法
公开(公告)号：US07129169B2
公开(公告)日：2006-10-31
申请号：US10709534
申请日：2004-05-12
申请人： Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/44 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/7833
摘要： A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.
摘要翻译：一种用于形成用于半导体器件的金属硅化物接触的方法包括在衬底上形成难熔金属层，该衬底包括所述衬底的有源区和非有源区，并在难熔金属层上形成覆盖层。反面拉伸层形成在覆盖层上方，其中相对抗拉层选自材料，使得在相对拉伸层和盖层之间产生相对的方向应力，相对于难熔金属之间产生的方向应力层和盖层。

3. 发明申请

US20120207920A1 PROTECTING A MOLD HAVING A SUBSTANTIALLY PLANAR SURFACE PROVIDED WITH A PLURALITY OF MOLD CAVITIES 失效
标题翻译：保护拥有大量模具CAE的大型平面表面的模具
公开(公告)号：US20120207920A1
公开(公告)日：2012-08-16
申请号：US13453371
申请日：2012-04-23
申请人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
发明人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
IPC分类号： B28B7/34
CPC分类号： H01L24/742 , H01L24/11 , H01L24/13 , H01L2224/11003 , H01L2224/131 , H01L2924/1431 , H01L2924/15788 , H01L2924/181 , H05K3/3478 , H01L2924/014 , H01L2924/00
摘要： A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.
摘要翻译：一种保护模具的方法，该模具具有设置有多个模腔的至少一个基本平坦的表面，包括将多个心轴插入到多个模腔中的相应的模腔中，将一层模具保护材料沉积在至少一个基本平面表面和多个心轴，并且从模具基板移除多个心轴。

4. 发明授权

US06497784B1 Semiconductor wafer edge bead removal method and tool 失效
标题翻译：半导体晶圆边缘除珠方法及工具
公开(公告)号：US06497784B1
公开(公告)日：2002-12-24
申请号：US09441862
申请日：1999-11-17
申请人： Bradley P. Jones , Viraj Y. Sardesai
发明人： Bradley P. Jones , Viraj Y. Sardesai
IPC分类号： H01L2100
CPC分类号： H01L21/6708 , H01L21/31053
摘要： A method for planarizing a dielectric layer on a semiconductor wafer is provided. In one aspect, the wafer is coated with a resist and the resist selectively removed forming an uncoated peripheral portion of the wafer. The partially coated wafer is then exposed to an etchant such as RIE to etch the dielectric material not covered by the resist and forming a profiled dielectric layer having a thinner peripheral dielectric portion and a remaining thicker original dielectric central portion. The profiled wafer is then planarized using CMP. The dielectric layer is typically SiO2, PSG, BSP, or BPSG. In another method and apparatus of the invention, a dielectric coated wafer is secured to a rotating turntable and a liquid etchant sprayed at the periphery of the wafer from a distribution conduit to etch and remove dielectric from a circumferential edge of the wafer forming a profiled dielectric layer as above which is then planarized by CMP. In another aspect of the invention, a CMP polished semiconductor wafer having an edge bead is planarized by polishing only the edge bead of the dielectric layer using a special polishing tool or a CMP apparatus to remove the edge bead from the dielectric layer. Planarized semiconductor wafers made using the method and apparatus of the invention are also provided.
摘要翻译：提供了一种用于平坦化半导体晶片上的电介质层的方法。在一个方面，晶片被涂覆有抗蚀剂，并且抗蚀剂被选择性地去除，形成晶片的未涂覆的周边部分。然后将部分涂覆的晶片暴露于诸如RIE的蚀刻剂以蚀刻未被抗蚀剂覆盖的介电材料，并形成具有更薄的外围电介质部分和剩余较厚的原始介电中心部分的异型电介质层。然后使用CMP对异型晶片进行平面化。电介质层通常是SiO 2，PSG，BSP或BPSG。在本发明的另一种方法和装置中，将电介质涂覆的晶片固定到旋转转盘和从分配导管在晶片周边喷射的液体蚀刻剂，以从晶圆的周边边缘蚀刻并去除电介质，从而形成异型电介质层，然后通过CMP平坦化。在本发明的另一方面，通过使用特殊的抛光工具或CMP装置仅抛光电介质层的边缘珠来平坦化具有边缘珠的CMP抛光的半导体晶片，以从电介质层去除边缘珠。还提供了使用本发明的方法和装置制造的平面化的半导体晶片。

5. 发明申请

US20110079702A1 FORMING A PROTECTIVE LAYER ON A MOLD AND MOLD HAVING A PROTECTIVE LAYER 审中-公开
标题翻译：在保护层模具和模具上形成保护层
公开(公告)号：US20110079702A1
公开(公告)日：2011-04-07
申请号：US12573904
申请日：2009-10-06
申请人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
发明人： Bradley P. Jones , Sarah H. Knickerbocker , Richard P. Volant
IPC分类号： B28B7/36 , B28B7/38 , B44C1/22
CPC分类号： H01L24/742 , H01L24/11 , H01L24/13 , H01L2224/11003 , H01L2224/131 , H01L2924/1431 , H01L2924/15788 , H01L2924/181 , H05K3/3478 , H01L2924/014 , H01L2924/00
摘要： A method of forming a mold having a protective layer includes forming a mold substrate having at least one substantially planar surface, depositing a layer of mold protection material onto the at least one substantially planar surface, and etching a plurality of cavities into the at least one substantially planar surface through the mold protection layer.
摘要翻译：一种形成具有保护层的模具的方法包括形成具有至少一个基本平坦的表面的模具基底，将一层模具保护材料沉积在所述至少一个基本平坦的表面上，以及将多个模腔蚀刻成至少一个基本平坦的表面通过模具保护层。

6. 发明授权

US07369911B1 Methods, systems, and computer program products for managing movement of work-in-process materials in an automated manufacturing environment 失效
标题翻译：用于管理自动化制造环境中工件在线材料的移动的方法，系统和计算机程序产品
公开(公告)号：US07369911B1
公开(公告)日：2008-05-06
申请号：US11621693
申请日：2007-01-10
申请人： Richard P. Volant , Bradley P. Jones , Sameer T. Shikalgar , Michael J. Toner , Yutong Wu
发明人： Richard P. Volant , Bradley P. Jones , Sameer T. Shikalgar , Michael J. Toner , Yutong Wu
IPC分类号： G06F19/00
CPC分类号： G06Q50/04 , G06Q10/06 , Y02P80/40 , Y02P90/30 , Y02P90/86
摘要： Methods, systems, and computer program products for managing movement of work-in-process materials between processing units in an automated manufacturing environment are provided. A system includes a host system in communication with a work-in-process (WIP) material lot. The system also includes an application executing on the host. The application implements a method that includes tracking a position of the WIP material lot, receiving a list of the processing units designated to be inoperative during a down time, and receiving a start time and a duration of the down time. The method also includes determining a maximum dwell time for each of the designated processing units and scheduling movement of the WIP material lot during an interim between a current time and the start time of the down time based on current position of the work-in-process material lot, the current time, the start time and duration of the down time, and the maximum dwell time.
摘要翻译：提供了用于管理在自动化制造环境中的处理单元之间的在制品材料的移动的方法，系统和计算机程序产品。系统包括与工件在制品（WIP）材料批次通信的主机系统。该系统还包括在主机上执行的应用程序。应用程序实现一种方法，其包括跟踪WIP物料批次的位置，接收在停机期间被指定为不起作用的处理单元的列表，以及接收停机时间的开始时间和持续时间。该方法还包括确定每个指定处理单元的最大驻留时间，并根据当前工作中的位置在当前时间与停机时间的开始时间间隔期间调度WIP材料批次的移动材料批次，当前时间，停机时间的开始时间和持续时间以及最长停留时间。

7. 发明申请

US20090181532A1 INTEGRATION SCHEME FOR EXTENSION OF VIA OPENING DEPTH 审中-公开
标题翻译：通过开放深度扩展的整合方案
公开(公告)号：US20090181532A1
公开(公告)日：2009-07-16
申请号：US11971996
申请日：2008-01-10
申请人： David P. Colon , Bradley P. Jones , Ramona Kei , Raymond G. Knauss , Richard P. Volant , Yun-Yu Wang
发明人： David P. Colon , Bradley P. Jones , Ramona Kei , Raymond G. Knauss , Richard P. Volant , Yun-Yu Wang
IPC分类号： H01L21/44
CPC分类号： H01L24/03 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05187 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/00014
摘要： An interconnect structure having an incomplete via opening is processed to deepen a via opening and to expose a metal line. In case the interconnect structure comprises a metal pad or a blanket metal layer, the metal pad or the metal layer is removed selective to an underlying dielectric layer to expose the incomplete via opening. Another dielectric layer is formed within the incomplete via opening to compensated for differences in the total dielectric thickness above the metal line relative to an optimal dielectric stack. A photoresist is applied thereupon and patterned. An anisotropic etch process for formation of a normal via opening may be employed with no or minimal modification to form a proper via opening and to expose the metal line. A metal pad is formed upon the metal line so that electrical contact is provided between the metal pad and the metal line.
摘要翻译：处理具有不完全通孔的互连结构以加深通孔开口并露出金属线。在互连结构包括金属焊盘或覆盖金属层的情况下，金属焊盘或金属层被选择性地移除到下面的电介质层以暴露不完全通孔。在不完全通孔内部形成另一个介电层，以补偿相对于最佳电介质叠层的金属线上方的总电介质厚度的差异。在其上施加光致抗蚀剂并图案化。可以采用用于形成正常通孔的各向异性蚀刻工艺，没有或最小的修改以形成适当的通孔开口并露出金属线。在金属线上形成金属焊盘，使得金属焊盘和金属线之间提供电接触。

8. 发明授权

US07480538B2 Methods, systems, and computer program products for managing movement of work-in-process materials in an automated manufacturing environment 失效
标题翻译：用于管理自动化制造环境中工件在线材料的移动的方法，系统和计算机程序产品
公开(公告)号：US07480538B2
公开(公告)日：2009-01-20
申请号：US11939792
申请日：2007-11-14
申请人： Richard P. Volant , Bradley P. Jones , Sameer T. Shikalgar , Michael J. Toner , Yutong Wu
发明人： Richard P. Volant , Bradley P. Jones , Sameer T. Shikalgar , Michael J. Toner , Yutong Wu
IPC分类号： G06F19/00
CPC分类号： G06Q50/04 , G06Q10/06 , Y02P80/40 , Y02P90/30 , Y02P90/86
摘要： Methods, systems, and computer program products for managing movement of work-in-process materials between processing units in an automated manufacturing environment are provided. A system includes a host system in communication with a work-in-process (WIP) material lot. The system also includes an application executing on the host. The application implements a method that includes tracking a position of the WIP material lot, receiving a list of the processing units designated to be inoperative during a down time, and receiving a start time and a duration of the down time. The method also includes determining a maximum dwell time for each of the designated processing units and scheduling movement of the WIP material lot during an interim between a current time and the start time of the down time based on current position of the work-in-process material lot, the current time, the start time and duration of the down time, and the maximum dwell time.
摘要翻译：提供了用于管理在自动化制造环境中的处理单元之间的在制品材料的移动的方法，系统和计算机程序产品。系统包括与工件在制品（WIP）材料批次通信的主机系统。该系统还包括在主机上执行的应用程序。应用程序实现一种方法，其包括跟踪WIP物料批次的位置，接收在停机期间被指定为不起作用的处理单元的列表，以及接收停机时间的开始时间和持续时间。该方法还包括确定每个指定处理单元的最大驻留时间，并根据当前工作中的位置在当前时间与停机时间的开始时间间隔期间调度WIP材料批次的移动材料批次，当前时间，停机时间的开始时间和持续时间以及最长停留时间。

9. 发明授权

US6117778A Semiconductor wafer edge bead removal method and tool 失效
公开(公告)号：US6117778A
公开(公告)日：2000-09-12
申请号：US021762
申请日：1998-02-11
申请人： Bradley P. Jones , Viraj Y. Sardesai
发明人： Bradley P. Jones , Viraj Y. Sardesai
IPC分类号： H01L21/00 , H01L21/3105 , H01L21/302
CPC分类号： H01L21/6708 , H01L21/31053
摘要： A method for planarizing a dielectric layer on a semiconductor wafer is provided. In one aspect, the wafer is coated with a resist and the resist selectively removed forming an uncoated peripheral portion of the wafer. The partially coated wafer is then exposed to an etchant such as RIE to etch the dielectric material not covered by the resist and forming a profiled dielectric layer having a thinner peripheral dielectric portion and a remaining thicker original dielectric central portion. The profiled wafer is then planarized using CMP. The dielectric layer is typically SiO.sub.2, PSG, BSP, or BPSG. In another method and apparatus of the invention, a dielectric coated wafer is secured to a rotating turntable and a liquid etchant sprayed at the periphery of the wafer from a distribution conduit to etch and remove dielectric from a circumferential edge of the wafer forming a profiled dielectric layer as above which is then planarized by CMP. In another aspect of the invention, a CMP polished semiconductor wafer having an edge bead is planarized by polishing only the edge bead of the dielectric layer using a special polishing tool or a CMP apparatus to remove the edge bead from the dielectric layer. Planarized semiconductor wafers made using the method and apparatus of the invention are also provided.

10. 发明授权

US5985768A Method of forming a semiconductor 失效
标题翻译：形成半导体的方法
公开(公告)号：US5985768A
公开(公告)日：1999-11-16
申请号：US845972
申请日：1997-04-30
申请人： Anthony C. Speranza , Bradley P. Jones
发明人： Anthony C. Speranza , Bradley P. Jones
IPC分类号： H01L21/8238 , H01L21/8242 , H01L21/31
CPC分类号： H01L21/823835 , H01L27/10894
摘要： The present invention discloses a method of doping and preventing silicide formation in selective areas of a polysilicon gate in MOS, PMOS, NMOS or CMOS manufacturing technologies. The process includes the steps of: depositing a non-conformal dopant containing layer on the top surface of the body and the top surface of the polysilicon gate; removing a portion of the non-conformal dopant containing layer to expose the top surface of the polysilicon gate; and heating to diffuse dopant from the dopant containing layer. Silicidation is then provided by depositing a metal layer and annealing the metal layer. As a first alternative method, the heating and removing step may be reversed. As a second alternative method, after removal of the non-conformal layer, a metal layer can be deposited followed by a combination anneal of the metal layer and non-conformal dopant containing layer.
摘要翻译：本发明公开了一种在MOS，PMOS，NMOS或CMOS制造技术中掺杂并防止在多晶硅栅极的选择区域中形成硅化物的方法。该方法包括以下步骤：在主体的顶表面和多晶硅栅极的顶表面上沉积非共形掺杂剂含量层; 去除所述非共形掺杂剂层的一部分以暴露所述多晶硅栅极的顶表面; 并且从掺杂剂层加热以扩散掺杂剂。然后通过沉积金属层并退火金属层来提供硅化。作为第一替代方法，加热和去除步骤可以颠倒。作为第二替代方法，在去除非保形层之后，可以沉积金属层，接着进行金属层和非保形掺杂剂层的组合退火。

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