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31. 发明授权

US08624295B2 SRAM devices utilizing strained-channel transistors and methods of manufacture 有权
标题翻译：使用应变通道晶体管的SRAM器件和制造方法
公开(公告)号：US08624295B2
公开(公告)日：2014-01-07
申请号：US12052389
申请日：2008-03-20
申请人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L21/02 , H01L21/762 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.
摘要翻译：提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。绝缘层基本上从半导体衬底表面升高。升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。

32. 发明授权

US08558278B2 Strained transistor with optimized drive current and method of forming 有权
标题翻译：应变晶体管具有优化的驱动电流和成型方法
公开(公告)号：US08558278B2
公开(公告)日：2013-10-15
申请号：US11849798
申请日：2007-09-04
申请人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.
摘要翻译：应变感应层形成在MOS器件的顶部，以增加沟道区中的载流子迁移率。在优选实施例中，应变诱导层的尺寸可导致优化的驱动电流增加和改进的NMOS和PMOS器件中的驱动电流均匀性。优选实施例的优点是在不添加复杂的处理步骤的情况下获得改进的设备性能。优选实施例的另一个优点是附加的处理步骤可以容易地集成到已知的CMOS工艺流程中。此外，创建定义拉伸和压缩应变诱导层的光罩不需要对现有设计数据库进行额外的设计工作。

33. 发明授权

US08368136B2 Integrating a capacitor in a metal gate last process 有权
标题翻译：将电容器集成在金属栅极最后工艺中
公开(公告)号：US08368136B2
公开(公告)日：2013-02-05
申请号：US12256132
申请日：2008-10-22
申请人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry Chuang , Tzung-Chi Lee , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L27/04
CPC分类号： H01L27/0629 , H01L27/11 , H01L29/94
摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料电极。

34. 发明授权

US08048752B2 Spacer shape engineering for void-free gap-filling process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US08048752B2
公开(公告)日：2011-11-01
申请号：US12179395
申请日：2008-07-24
申请人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

35. 发明申请

US20110227189A1 Dishing-Free Gap-Filling with Multiple CMPs 有权
标题翻译：无间隙填充多个CMP
公开(公告)号：US20110227189A1
公开(公告)日：2011-09-22
申请号：US13151666
申请日：2011-06-02
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L27/04
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

36. 发明申请

US20100117190A1 FUSE STRUCTURE FOR INTERGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于集成电路设备的保险丝结构
公开(公告)号：US20100117190A1
公开(公告)日：2010-05-13
申请号：US12270717
申请日：2008-11-13
申请人： Harry CHUANG , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
发明人： Harry CHUANG , Kong-Beng Thei , Sheng-Chen Chung , Mong-Song Liang
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for an IC device and methods of fabricating the structure are provided. The fuse structure comprises a metal-containing conductive strip formed over a portion of a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate, covering the conductive strip. A first interconnect and a second interconnect are formed in vias extending through the dielectric layer, each physically and electrically connecting to a part of the conductive layer. First and second wiring structures are formed over the dielectric layer in electrical contact with the first and second interconnects respectively. The contact area between one of the interconnects and the strip is chosen so that electromigration will occur when a pre-selected current is applied to the fuse structure.
摘要翻译：提供了一种用于IC器件的熔丝结构及其制造方法。熔丝结构包括在半导体衬底的一部分上形成的含金属的导电条。在半导体衬底上形成介电层，覆盖导电带。第一互连和第二互连形成在延伸穿过介电层的通孔中，每个物理和电连接到导电层的一部分。第一和第二布线结构形成在电介质层上，分别与第一和第二互连电接触。选择互连和条之一之间的接触面积，使得当将预选电流施加到熔丝结构时，将发生电迁移。

37. 发明申请

US20100013029A1 Structure and a Method of Manufacture for Low Resistance NiSix 有权
标题翻译：低电阻NiSix的结构和制造方法
公开(公告)号：US20100013029A1
公开(公告)日：2010-01-21
申请号：US12176133
申请日：2008-07-18
申请人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Keh-Chiang Ku , Kong-Beng Thei , Mong Song Liang
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L29/4983 , H01L21/28518 , H01L21/28525 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.
摘要翻译：提出了一种用于形成金属硅化物的器件和方法。在基板上形成包括栅极区域，源极区域和漏极区域的器件。在基板上设置金属，接着进行第一退火，在栅极区域，源极区域和漏极区域中的至少一个上形成金属硅化物。将未反应的金属从基材上除去。金属硅化物被注入原子。植入物之后是衬底的超退火。

38. 发明申请

US20100001369A1 DEVICE LAYOUT FOR GATE LAST PROCESS 有权
标题翻译：上一个流程的设备布局
公开(公告)号：US20100001369A1
公开(公告)日：2010-01-07
申请号：US12471091
申请日：2009-05-22
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要： A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

39. 发明申请

US20090236633A1 SRAM Devices Utilizing Strained-Channel Transistors and Methods of Manufacture 有权
标题翻译：使用应变通道晶体管的SRAM器件和制造方法
公开(公告)号：US20090236633A1
公开(公告)日：2009-09-24
申请号：US12052389
申请日：2008-03-20
申请人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Hung-Chih Tsai , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L27/092
CPC分类号： H01L21/8238 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.
摘要翻译：提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。绝缘层基本上从半导体衬底表面升高。升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。

40. 发明申请

US20080169484A1 Strained Transistor with Optimized Drive Current and Method of Forming 有权
标题翻译：应变晶体管具有优化的驱动电流和形成方法
公开(公告)号：US20080169484A1
公开(公告)日：2008-07-17
申请号：US11849798
申请日：2007-09-04
申请人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Wen-Huei Guo , Mong Song Liang
IPC分类号： H01L27/092 , H01L29/778
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.
摘要翻译：应变感应层形成在MOS器件的顶部，以增加沟道区中的载流子迁移率。在优选实施例中，应变诱导层的尺寸可导致优化的驱动电流增加和改进的NMOS和PMOS器件中的驱动电流均匀性。优选实施例的优点是在不添加复杂的处理步骤的情况下获得改进的设备性能。优选实施例的另一个优点是附加的处理步骤可以容易地集成到已知的CMOS工艺流程中。此外，创建定义拉伸和压缩应变诱导层的光罩不需要对现有设计数据库进行额外的设计工作。

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