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31. 发明申请

US20060043503A1 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US20060043503A1
公开(公告)日：2006-03-02
申请号：US11237396
申请日：2005-09-28
申请人： Kunal Parekh , H. Manning
发明人： Kunal Parekh , H. Manning
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L29/6653 , H01L21/28114 , H01L21/28238 , H01L21/823456 , H01L21/823468 , H01L29/66553 , H01L29/66583
摘要： The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of dielectric material being within an opening. A gateline material is formed within the opening and over the thin and thicker segments of dielectric material. The construction comprising the gateline material over the thin and thicker segments of dielectric material can be supported by a semiconductor substrate having a primary surface which defines a horizontal direction. The thin and thicker segments of dielectric material can comprise upper surfaces substantially parallel to the primary surface of the substrate, and can join to one another at steps having primary surfaces substantially orthogonal to the primary surface of the substrate.
摘要翻译：本发明包括半导体构造，形成栅极的方法以及形成晶体管结构的方法。本发明可以包括例如形成盖茨线的镶嵌方法。介电材料的薄段形成在介电材料的两个更厚的部分之间，其中较薄和较厚的电介质材料段在开口内。在开口内和电介质材料的较薄和较厚的部分之上形成栅栏材料。包含电介质材料的较薄和较厚部分上的栅极材料的结构可由具有限定水平方向的主表面的半导体衬底支撑。电介质材料的薄而较厚的部分可以包括基本上平行于衬底的主表面的上表面，并且可以在具有基本上垂直于衬底的主表面的主表面的台阶上彼此连接。

32. 发明申请

US20060043467A1 Stepped gate configuration for non-volatile memory 有权
公开(公告)号：US20060043467A1
公开(公告)日：2006-03-02
申请号：US11257637
申请日：2005-10-25
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , G11C16/0416 , G11C16/0483 , H01L29/7923
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

33. 发明申请

US20060043462A1 Stepped gate configuration for non-volatile memory 审中-公开
标题翻译：非易失性存储器的步进门配置
公开(公告)号：US20060043462A1
公开(公告)日：2006-03-02
申请号：US10928082
申请日：2004-08-27
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , G11C16/0416 , G11C16/0483 , H01L29/40117
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.
摘要翻译：本文公开了具有带梯级栅极电介质的场效应晶体管及其制造方法的存储器件。阶梯式栅极电介质形成在半导体衬底上，由一对由栅极电介质隔开的电荷俘获电介质组成; 在其上形成栅极导体。源极和漏极区域形成在该对电荷俘获电介质的相对侧上的半导体衬底中。存储器件通过在半导体衬底上形成电荷俘获电介质层而制成。通过电荷捕获电介质层形成沟槽以暴露半导体衬底的一部分。栅极电介质层形成在沟槽内，栅极导体层形成在电荷俘获和栅极电介质层上。

34. 发明授权

US06885542B2 Capacitor structure 失效
标题翻译：电容结构
公开(公告)号：US06885542B2
公开(公告)日：2005-04-26
申请号：US10932503
申请日：2004-09-02
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L21/02 , H01L21/8242 , H01G4/228
CPC分类号： H01L27/10852 , H01L28/82
摘要： A capacitor is formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.
摘要翻译：电容器形成为具有大致凹入的形状并且具有可选的折叠或回旋表面。凹形形状在小体积内优化表面积，从而使电容器能够保持大量电荷，从而有助于微电子领域中的增加的小型化努力。电容器以与电致密DRAM阵列一致的微电子方式制造。制造方法包括具有在半导体衬底表面上方延伸的存储节点的堆叠构造。

35. 发明授权

US06459116B1 Capacitor structure 有权
公开(公告)号：US06459116B1
公开(公告)日：2002-10-01
申请号：US09283606
申请日：1999-04-01
申请人： Zhiqiang Wu , Kunal Parekh , Li Li
发明人： Zhiqiang Wu , Kunal Parekh , Li Li
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L28/82
摘要： The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

36. 发明授权

US5789304A Method of forming a capacitor 失效
公开(公告)号：US5789304A
公开(公告)日：1998-08-04
申请号：US741832
申请日：1996-10-31
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.

37. 发明授权

US08716116B2 Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline 有权
标题翻译：使用垂直集成的凹槽接入设备和数字线形成DRAM阵列的方法
公开(公告)号：US08716116B2
公开(公告)日：2014-05-06
申请号：US12721373
申请日：2010-03-10
申请人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
发明人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L27/108 , H01L27/10882 , H01L27/10885
摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
摘要翻译：公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

38. 发明授权

US08497541B2 Memory having buried digit lines and methods of making the same 有权
标题翻译：具有埋置数字线的存储器和制作相同的方法
公开(公告)号：US08497541B2
公开(公告)日：2013-07-30
申请号：US12721404
申请日：2010-03-10
申请人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
发明人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
IPC分类号： H01L27/108
CPC分类号： G11C5/06 , G11C5/025 , G11C11/405 , H01L27/1052 , H01L27/108 , H01L27/10879 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
摘要翻译：具有存储单元的存储器阵列及其形成方法。存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置，在第二水平平面体积之上的第三水平平面体积。存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

39. 发明授权

US07968460B2 Semiconductor with through-substrate interconnect 有权
标题翻译：半导体与通孔基板互连
公开(公告)号：US07968460B2
公开(公告)日：2011-06-28
申请号：US12142251
申请日：2008-06-19
申请人： Kyle Kirby , Kunal Parekh
发明人： Kyle Kirby , Kunal Parekh
IPC分类号： H01L21/44
CPC分类号： H01L21/743 , H01L21/26513 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/49816 , H01L27/0694 , H01L27/10888 , H01L27/10894 , H01L29/66568 , H01L29/78 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548
摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
摘要翻译：描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部金属填充通孔的区域。

40. 发明申请

US20080119053A1 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
标题翻译：在存储器件上制造隔板间隔的方法以及包含其的装置
公开(公告)号：US20080119053A1
公开(公告)日：2008-05-22
申请号：US12020752
申请日：2008-01-28
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/311
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

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