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1. 发明授权

US5962885A Method of forming a capacitor and a capacitor construction 失效
标题翻译：电容器结构
公开(公告)号：US5962885A
公开(公告)日：1999-10-05
申请号：US935966
申请日：1997-09-23
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： The invention encompasses capacitor constructions. In one aspect, the invention includes a stacked capacitor construction comprising: a) a substrate; b) an electrically conductive runner provided on the substrate, the runner having an outer conductive surface; c) a node on the substrate adjacent the electrically conductive runner; d) an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node adjacent the conductive runner, the pillar having an outer surface; e) an electrically conductive storage node container layer in electrical connection with the pillar; f) a capacitor dielectric layer over the capacitor storage node layer; and g) an electrically conductive outer capacitor plate over the capacitor dielectric layer; and h) the pillar outer surface being elevationally inward of the runner outer surface.
摘要翻译：本发明包括电容器结构。一方面，本发明包括堆叠式电容器结构，其包括：a）衬底; b）设置在所述基底上的导电流道，所述流道具有外导电表面; c）邻近导电流道的衬底上的节点; d）与所述节点电连接的导电柱，所述柱相对于邻近导电流道的节点向外突出，所述柱具有外表面; e）与所述支柱电连接的导电存储节点容器层; f）电容器存储节点层上的电容器介电层; 和g）电容器介电层上的导电外电容器板; 以及h）所述柱外表面位于所述流道外表面的正上方。

2. 发明授权

US5789304A Method of forming a capacitor 失效
公开(公告)号：US5789304A
公开(公告)日：1998-08-04
申请号：US741832
申请日：1996-10-31
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.

3. 发明授权

US5604147A Method of forming a cylindrical container stacked capacitor 失效
标题翻译：形成圆柱形容器堆叠电容器的方法
公开(公告)号：US5604147A
公开(公告)日：1997-02-18
申请号：US440212
申请日：1995-05-12
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.
摘要翻译：形成层叠容器电容器的半导体处理方法包括：a）相对于衬底提供一对隔开的导电流道，所述导电流道分别具有电绝缘侧壁间隔件和电绝缘帽，所述帽具有相应的外表面; b）在要与电容器进行电连接的流道之间提供节点; c）提供与所述节点电连接的导电柱，所述柱相对于所述流道之间的节点向外突出，并且具有位于两个流道盖之外的第一外表面，所述柱完全填充所述一对流道之间的空间，支柱所在的位置; d）在盖和导电柱之外提供绝缘介电层; e）蚀刻穿过所述绝缘介电层的容器开口以向外暴露所述导电柱第一外表面; f）蚀刻暴露的导电柱以限定比第一外表面更靠近节点的支柱第二外表面并加深容器开口; g）在第二外导电柱表面之上的容器开口内提供导电存储节点容器层; h）在所述电容器存储节点层上提供电容器介电层; 以及i）在所述电容器介电层上方提供导电的外部电容器板。还公开了这种电容器结构。

4. 发明授权

US6010941A Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US6010941A
公开(公告)日：2000-01-04
申请号：US112629
申请日：1998-07-09
申请人： Mark Fischer , Mark Jost , Kunal Parekh
发明人： Mark Fischer , Mark Jost , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/40 , Y10S148/02
摘要： A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed conductive pillar to define a pillar second outer surface which is closer to the node than the pillar first outer surface and to deepen the container opening; g) providing an electrically conductive storage node container layer within the container opening over the second outer conductive pillar surface; h) providing a capacitor dielectric layer over the capacitor storage node layer; and i) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. Such a capacitor construction is also disclosed.
摘要翻译：形成层叠容器电容器的半导体处理方法包括：a）相对于衬底提供一对隔开的导电流道，所述导电流道分别具有电绝缘侧壁间隔件和电绝缘帽，所述帽具有相应的外表面; b）在要与电容器进行电连接的流道之间提供节点; c）提供与所述节点电连接的导电柱，所述柱相对于所述流道之间的节点向外突出，并且具有位于两个流道盖之外的第一外表面，所述柱完全填充所述一对流道之间的空间，支柱所在的位置; d）在盖和导电柱之外提供绝缘介电层; e）蚀刻通过所述绝缘介电层的容器开口以向外暴露所述导电柱第一外表面; f）蚀刻暴露的导电柱以限定比第一外表面更靠近节点的支柱第二外表面并加深容器开口; g）在第二外导电柱表面之上的容器开口内提供导电存储节点容器层; h）在所述电容器存储节点层上提供电容器介电层; 以及i）在所述电容器介电层上方提供导电的外部电容器板。还公开了这种电容器结构。

5. 发明授权

US5686747A Integrated circuits comprising interconnecting plugs 失效
标题翻译：包括互连插头的集成电路
公开(公告)号：US5686747A
公开(公告)日：1997-11-11
申请号：US700320
申请日：1996-08-07
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108 , H01L29/41
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; e）有点线 f）位于所述位线和所述有效区域之间的介电绝缘层; g）延伸穿过绝缘层并将位线与另一有源区域电互连的位线插头，位线插头包括导电环形环。还公开了利用环形互连环的集成电路，超越了存储器件。还公开了具有另外的径向向内的绝缘环形环和导电环的这种结构。还公开了一种在具有这种环的存储器单元的电容器阵列上形成位线的方法。

6. 发明授权

US5821140A Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
公开(公告)号：US5821140A
公开(公告)日：1998-10-13
申请号：US732067
申请日：1996-10-16
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.

7. 发明授权

US5563089A Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells 失效
标题翻译：在存储器单元的电容器阵列上形成位线的方法以及存储器单元的电容器阵列上的位线阵列
公开(公告)号：US5563089A
公开(公告)日：1996-10-08
申请号：US394545
申请日：1995-02-22
申请人： Mark Jost , Charles H. Dennison , Kunal Parekh
发明人： Mark Jost , Charles H. Dennison , Kunal Parekh
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76885 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002 , Y10S257/915
摘要： A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with one of the active areas; e) a bit line; f) a dielectric insulating layer positioned intermediate the bit line and the active areas; g) a bit line plug extending through the insulating layer and electrically interconnecting the bit line with the other active area, the bit line plug comprising an electrically conductive annular ring. Integrated circuitry, beyond memory devices, utilizing an annular interconnection ring are also disclosed. Such constructions having additional radially inward insulating annular rings and conductive rings are also disclosed. A method of forming a bit line over capacitor array of memory cells having such rings is also disclosed.
摘要翻译：半导体存储器件包括：a）半导体衬底; b）位于半导体衬底外侧的场效应晶体管栅极; c）在栅极的相对侧上形成在半导体衬底内的相对的有源区; d）与有源区域之一电连接的电容器; e）有点线 f）位于所述位线和所述有效区域之间的介电绝缘层; g）延伸穿过绝缘层并将位线与另一有源区域电互连的位线插头，位线插头包括导电环形环。还公开了利用环形互连环的集成电路，超越了存储器件。还公开了具有另外的径向向内的绝缘环形环和导电环的这种结构。还公开了一种在具有这种环的存储器单元的电容器阵列上形成位线的方法。

8. 发明授权

US6083803A Semiconductor processing methods of forming a conductive projection and methods of increasing alignment tolerances 失效
公开(公告)号：US6083803A
公开(公告)日：2000-07-04
申请号：US32254
申请日：1998-02-27
申请人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
发明人： Mark Fischer , John K. Zahurak , Thomas M. Graettinger , Kunal Parekh
IPC分类号： H01L21/302 , G03F7/075 , G03F7/16 , H01L21/3065 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10888 , G03F7/0757 , G03F7/167 , H01L21/76838 , H01L27/10852
摘要： Semiconductor processing methods of forming conductive projections and methods of increasing alignment tolerances are described. In one implementation, a conductive projection is formed over a substrate surface area and includes an upper surface and a side surface joined therewith to define a corner region. The corner region of the conductive projection is subsequently beveled to increase an alignment tolerance relative thereto. In another implementation, a conductive plug is formed over a substrate node location between a pair of conductive lines and has an uppermost surface. Material of the conductive plug is unevenly removed to define a second uppermost surface, at least a portion of which is disposed elevationally higher than a conductive line. In one aspect, conductive plug material can be removed by facet etching the conductive plug. In another aspect, conductive plug material is unevenly doped with dopant, and conductive plug material containing greater concentrations of dopant is etched at a greater rate than plug material containing lower concentrations of dopant.

9. 发明申请

US20050218474A1 Use of DAR coating to modulate the efficiency of laser fuse blows 有权
标题翻译：使用DAR涂层来调节激光熔丝的效率
公开(公告)号：US20050218474A1
公开(公告)日：2005-10-06
申请号：US11140859
申请日：2005-05-31
申请人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
发明人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
IPC分类号： H01L21/82 , H01L21/8222 , H01L23/525 , H01L29/00
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
摘要翻译：本发明涉及一种激光熔丝。激光熔丝包括包含导热材料的元件。保险丝还包括吸收元件，该吸收元件包括具有与热传导元件重叠的热或光吸收的可调节容量的材料。保险丝还包括覆盖并包围导热元件和吸收元件的外绝缘元件。

10. 发明申请

US20060263987A1 Methods of forming fusible devices 审中-公开
标题翻译：形成易熔装置的方法
公开(公告)号：US20060263987A1
公开(公告)日：2006-11-23
申请号：US11496251
申请日：2006-07-31
申请人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
发明人： Mark Fischer , Zhiping Yin , Thomas Glass , Kunal Parekh , Gurtej Sandhu
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse. The laser fuse comprises an element comprising a heat conductive material. The fuse also includes an absorption element comprising a material with an adjustable capacity for heat or light absorption that overlays the heat conductive element. The fuse also includes an outer insulating element that overlays and encloses the heat conductive element and the absorption element.
摘要翻译：本发明涉及一种激光熔丝。激光熔丝包括包含导热材料的元件。保险丝还包括吸收元件，该吸收元件包括具有与热传导元件重叠的热或光吸收的可调容量的材料。保险丝还包括覆盖并包围导热元件和吸收元件的外绝缘元件。

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