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1. 发明申请

US20060043468A1 Stepped gate configuration for non-volatile memory 审中-公开
公开(公告)号：US20060043468A1
公开(公告)日：2006-03-02
申请号：US11257843
申请日：2005-10-25
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , G11C16/0416 , G11C16/0483 , H01L29/40117
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

2. 发明申请

US20060038244A1 Gated field effect devices 失效
标题翻译：门控场效应器件
公开(公告)号：US20060038244A1
公开(公告)日：2006-02-23
申请号：US11253461
申请日：2005-10-19
申请人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
发明人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
IPC分类号： H01L29/94
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

3. 发明申请

US20060258086A1 Methods of forming vertical transistor structures 有权
公开(公告)号：US20060258086A1
公开(公告)日：2006-11-16
申请号：US11486512
申请日：2006-07-13
申请人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
发明人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

4. 发明申请

US20060043466A1 Stepped gate configuration for non-volatile memory 有权
公开(公告)号：US20060043466A1
公开(公告)日：2006-03-02
申请号：US11257636
申请日：2005-10-25
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , G11C16/0416 , G11C16/0483 , H01L29/7923
摘要： A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric is formed on a semiconductor substrate and consists of a pair of charge trapping dielectrics separated by a gate dielectric; a gate conductor is formed thereover. Source and drain areas are formed in the semiconductor substrate on opposing sides of the pair of charge trapping dielectrics. The memory device is made by forming a charge trapping dielectric layer on a semiconductor substrate. A trench is formed through the charge trapping dielectric layer to expose a portion of the semiconductor substrate. A gate dielectric layer is formed within the trench and a gate conductor layer is formed over the charge trapping and gate dielectric layers.

5. 发明申请

US20060258087A1 Methods of forming vertical transistor structures 有权
公开(公告)号：US20060258087A1
公开(公告)日：2006-11-16
申请号：US11486524
申请日：2006-07-13
申请人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
发明人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/425 , H01L21/8238
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.

6. 发明申请

US20060211208A1 Methods of forming gatelines and transistor devices 有权
公开(公告)号：US20060211208A1
公开(公告)日：2006-09-21
申请号：US11418556
申请日：2006-05-05
申请人： Kunal Parekh , H. Manning
发明人： Kunal Parekh , H. Manning
IPC分类号： H01L21/336
CPC分类号： H01L29/6653 , H01L21/28114 , H01L21/28238 , H01L21/823456 , H01L21/823468 , H01L29/66553 , H01L29/66583
摘要： The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of dielectric material being within an opening. A gateline material is formed within the opening and over the thin and thicker segments of dielectric material. The construction comprising the gateline material over the thin and thicker segments of dielectric material can be supported by a semiconductor substrate having a primary surface which defines a horizontal direction. The thin and thicker segments of dielectric material can comprise upper surfaces substantially parallel to the primary surface of the substrate, and can join to one another at steps having primary surfaces substantially orthogonal to the primary surface of the substrate.

7. 发明申请

US20060001072A1 Methods of forming a gated device 有权
标题翻译：形成门控装置的方法
公开(公告)号：US20060001072A1
公开(公告)日：2006-01-05
申请号：US11171873
申请日：2005-06-30
申请人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
发明人： Cem Basceri , H. Manning , Gurtej Sandhu , Kunal Parekh
IPC分类号： H01L21/8238 , H01L27/108 , H01L29/792
CPC分类号： H01L29/4983 , H01L21/28194 , H01L29/512 , H01L29/517
摘要： This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.
摘要翻译：本发明包括门控场效应器件，以及形成门控场效应器件的方法。在一种实施方案中，门控场效应器件包括在其间具有沟道区的一对源/漏区。在源极/漏极区域之间的沟道区域附近接收栅极。栅极在源极/漏极区之间具有栅极宽度。栅极电介质被接收在沟道区域和栅极之间。栅极电介质沿着栅极的宽度具有至少两个不同的区域。不同的区域由不同的材料表征，其有效地限定两个不同的区域以具有不同的介电常数k。考虑了其他方面和实现。

8. 发明申请

US20070037316A1 Memory cell contact using spacers 审中-公开
标题翻译：记忆单元接触使用垫片
公开(公告)号：US20070037316A1
公开(公告)日：2007-02-15
申请号：US11199252
申请日：2005-08-09
申请人： H. Manning , Kunal Parekh
发明人： H. Manning , Kunal Parekh
IPC分类号： H01L21/06
CPC分类号： H01L21/76831 , H01L21/76877 , H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/16
摘要： A method of forming contacts used in a memory device. The method involves forming a via in an insulating layer, forming spacers on sidewalls of the via, and filling the via with a conductive material. The resulting contact has rounded upper corners to improve the reliability of the memory device. Also disclosed is a subsequent recessing and refilling method to mitigate keyholes in the memory device contacts.
摘要翻译：一种在存储器件中形成触点的方法。该方法包括在绝缘层中形成通孔，在通孔的侧壁上形成间隔物，并用导电材料填充通孔。所产生的触点具有圆角的上角以提高存储器件的可靠性。还公开了一种随后的凹陷和补充方法来减轻存储器件触点中的键孔。

9. 发明申请

US20060046392A1 Methods of forming vertical transistor structures 审中-公开
标题翻译：形成垂直晶体管结构的方法
公开(公告)号：US20060046392A1
公开(公告)日：2006-03-02
申请号：US10928467
申请日：2004-08-26
申请人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
发明人： H. Manning , Kunal Parekh , Cem Basceri , Gurtej Sandhu
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/425 , H01L21/8242
CPC分类号： H01L29/66787 , H01L27/10808 , H01L27/10876
摘要： The invention includes methods in which an angled implant is utilized to self-align a source/drain region implant with the top edge of a gateline of a vertical transistor structure. The invention also includes methods in which an angled implant is utilized to implant dopant beneath the gateline of a vertical transistor structure. Vertical transistor structures formed in accordance with methodology of the present invention can be incorporated into various types of integrated circuitry, including, for example, DRAM arrays.
摘要翻译：本发明包括这样的方法，其中使用成角度的注入来使源极/漏极区域注入与垂直晶体管结构的天线的顶部边缘自对准。本发明还包括其中使用成角度的植入物以在垂直晶体管结构的栅极下注入掺杂剂的方法。根据本发明的方法形成的垂直晶体管结构可以结合到各种类型的集成电路中，包括例如DRAM阵列。

10. 发明申请

US20060043505A1 Semiconductor constructions, and methods of forming gatelines and transistor devices 有权
标题翻译：半导体结构，以及形成栅极和晶体管器件的方法
公开(公告)号：US20060043505A1
公开(公告)日：2006-03-02
申请号：US10928514
申请日：2004-08-27
申请人： Kunal Parekh , H. Manning
发明人： Kunal Parekh , H. Manning
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/6653 , H01L21/28114 , H01L21/28238 , H01L21/823456 , H01L21/823468 , H01L29/66553 , H01L29/66583
摘要： The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between two thicker segments of dielectric material, with the thin and thicker segments of dielectric material being within an opening. A gateline material is formed within the opening and over the thin and thicker segments of dielectric material. The construction comprising the gateline material over the thin and thicker segments of dielectric material can be supported by a semiconductor substrate having a primary surface which defines a horizontal direction. The thin and thicker segments of dielectric material can comprise upper surfaces substantially parallel to the primary surface of the substrate, and can join to one another at steps having primary surfaces substantially orthogonal to the primary surface of the substrate.
摘要翻译：本发明包括半导体构造，形成栅极的方法以及形成晶体管结构的方法。本发明可以包括例如形成盖茨线的镶嵌方法。介电材料的薄段形成在介电材料的两个更厚的部分之间，其中较薄和较厚的电介质材料段在开口内。在开口内和电介质材料的较薄和较厚的部分之上形成栅栏材料。包含电介质材料的较薄和较厚部分上的栅极材料的结构可由具有限定水平方向的主表面的半导体衬底支撑。电介质材料的薄而较厚的部分可以包括基本上平行于衬底的主表面的上表面，并且可以在具有基本上垂直于衬底的主表面的主表面的台阶上彼此连接。

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