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1. 发明申请

US20060263969A1 Method of manufacturing sidewall spacers on a memory device, and device comprising same 有权
公开(公告)号：US20060263969A1
公开(公告)日：2006-11-23
申请号：US11132472
申请日：2005-05-19
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/8244
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.

2. 发明申请

US20080119053A1 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
标题翻译：在存储器件上制造隔板间隔的方法以及包含其的装置
公开(公告)号：US20080119053A1
公开(公告)日：2008-05-22
申请号：US12020752
申请日：2008-01-28
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/311
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

3. 发明申请

US20070111436A1 METHOD OF MANUFACTURING SIDEWALL SPACERS ON A MEMORY DEVICE, AND DEVICE COMPRISING SAME 有权
标题翻译：在存储器件上制造隔板间隔的方法以及包含其的装置
公开(公告)号：US20070111436A1
公开(公告)日：2007-05-17
申请号：US11616511
申请日：2006-12-27
申请人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
发明人： David Hwang , Kunal Parekh , Michael Willett , Jigish Trivedi , Suraj Mathew , Greg Peterson
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/10897 , H01L27/11543
摘要： The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.
摘要翻译：本发明一般涉及在存储器件上制造侧壁间隔物的方法，以及包括这种侧壁间隔物的存储器件。在一个说明性实施例中，该方法包括在由存储器阵列和至少一个外围电路构成的存储器件上形成侧壁间隔物，该隔离物通过形成邻近存储器阵列中的字线结构的第一侧壁间隔物，第一侧壁间隔物具有第一厚度以及在所述外围电路中形成与所述晶体管结构相邻的第二侧壁间隔物，所述第二侧壁间隔物具有大于所述第一厚度的第二厚度，其中所述第一和第二侧壁间隔物包括来自单层间隔物材料的材料。在一个说明性实施例中，该装置包括由多个字线结构组成的存储器阵列，多个字线结构中的每一个具有与其相邻形成的第一侧壁间隔物，第一侧壁间隔物具有第一厚度，外围电路包括至少一个晶体管，其具有与其相邻形成的第二侧壁间隔物，所述第二侧壁间隔物具有大于第一厚度的第二厚度，所述第一和第二侧壁间隔物由来自单层间隔物材料的材料构成。

4. 发明申请

US20110220980A1 MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME 有权
标题翻译：带有数字数据线的存储器及其制造方法
公开(公告)号：US20110220980A1
公开(公告)日：2011-09-15
申请号：US12721404
申请日：2010-03-10
申请人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
发明人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： G11C5/06 , G11C5/025 , G11C11/405 , H01L27/1052 , H01L27/108 , H01L27/10879 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
摘要翻译：具有存储单元的存储器阵列及其形成方法。存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置，在第二水平平面体积之上的第三水平平面体积。存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

5. 发明授权

US08716116B2 Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline 有权
标题翻译：使用垂直集成的凹槽接入设备和数字线形成DRAM阵列的方法
公开(公告)号：US08716116B2
公开(公告)日：2014-05-06
申请号：US12721373
申请日：2010-03-10
申请人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
发明人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L27/108 , H01L27/10882 , H01L27/10885
摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
摘要翻译：公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

6. 发明授权

US08497541B2 Memory having buried digit lines and methods of making the same 有权
标题翻译：具有埋置数字线的存储器和制作相同的方法
公开(公告)号：US08497541B2
公开(公告)日：2013-07-30
申请号：US12721404
申请日：2010-03-10
申请人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
发明人： Kunal Parekh , David Hwang , Wen Kuei Huang , Kuo Chen Wang , Ching Kai Lin
IPC分类号： H01L27/108
CPC分类号： G11C5/06 , G11C5/025 , G11C11/405 , H01L27/1052 , H01L27/108 , H01L27/10879 , H01L29/66666 , H01L29/7827 , H01L29/785
摘要： A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
摘要翻译：具有存储单元的存储器阵列及其形成方法。存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置，在第二水平平面体积之上的第三水平平面体积。存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。

7. 发明申请

US20110220994A1 Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline 有权
标题翻译：形成具有垂直集成嵌入式接入设备和数字线的设备的DRAM阵列的方法
公开(公告)号：US20110220994A1
公开(公告)日：2011-09-15
申请号：US12721373
申请日：2010-03-10
申请人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
发明人： Kunal Parekh , Ceredig Roberts , Thy Tran , Jim Jozwiak , David Hwang
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/10891 , H01L27/108 , H01L27/10882 , H01L27/10885
摘要： A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.
摘要翻译：公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

8. 发明授权

US08090013B2 Method and system of providing a high speed Tomlinson-Harashima Precoder 有权
标题翻译：提供高速Tomlinson-Harashima Precoder的方法和系统
公开(公告)号：US08090013B2
公开(公告)日：2012-01-03
申请号：US12043751
申请日：2008-03-06
申请人： Arash Farhoodfar , Kishore Kota , Alan Kwentus , David Hwang
发明人： Arash Farhoodfar , Kishore Kota , Alan Kwentus , David Hwang
IPC分类号： H03H7/30 , H04B15/00 , H04N5/00
CPC分类号： H04L25/497 , H04L25/4975
摘要： Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.
摘要翻译：这里描述了至少一种用于实现高速Tomlinson-Harashima Precoder的方法和系统。该方法包括使用Tomlinson-Harashima预编码器的L抽头转置配置，并使用时钟信号对所述L系数和L状态变量进行处理，以便使用L抽头Tomlinson-Harashima Precoder，其中时钟信号具有等于离散时间采样序列的符号速率的一半的时钟速率。在代表性实施例中，L抽头Tomlinson-Harashima预编码器包括单个集成电路芯片，其中该集成电路芯片包括至少一个电路，用于通过使用离散的时钟来处理使用L个系数和L个状态变量的离散时间采样序列使用时钟速率为离散时间采样序列的符号率的一半的时钟信号的时间采样序列。

9. 发明申请

US20110140187A1 Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, And DRAM Cells 有权
标题翻译：形成垂直场效应晶体管，垂直场效应晶体管和DRAM单元的方法
公开(公告)号：US20110140187A1
公开(公告)日：2011-06-16
申请号：US13036725
申请日：2011-02-28
申请人： Larson Lindholm , David Hwang
发明人： Larson Lindholm , David Hwang
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66666 , H01L27/0207 , H01L27/10876 , H01L29/0657 , H01L29/0692 , H01L29/7827
摘要： A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.
摘要翻译：形成垂直场效应晶体管的方法包括将开口蚀刻成半导体材料。开口底座的侧壁和径向最外部的部分衬有掩模材料。半导体材料柱外延生长在与开口底部的半导体材料的掩模材料相邻的开口内。至少一些掩模材料从开口去除。栅极电介质围绕柱径向地形成。导电栅极材料围绕栅极电介质径向地形成。柱的上部形成为包括垂直晶体管的一个源极/漏极区域。接收在上部下方的柱的半导体材料形成为包括垂直晶体管的沟道区。与开口相邻的半导体材料形成为包括垂直晶体管的另一个源极/漏极区域。考虑了其他方面和实现。

10. 发明授权

US07026834B2 Multiple two axis floating probe block assembly using split probe block 失效
标题翻译：多个双轴浮动探头块组件使用分离探针块
公开(公告)号：US07026834B2
公开(公告)日：2006-04-11
申请号：US11222286
申请日：2005-09-08
申请人： David Hwang
发明人： David Hwang
IPC分类号： G01R31/26
CPC分类号： G01R1/0416
摘要： A novel probe block assembly which independently floats multiple probe blocks in a single frame is presented. The independently floating probe blocks allow multiple probes to align independently with respective multiple mating features on a device under test. The use of a single frame allows multiple insertion probe testing via one actuation motion.
摘要翻译：提出了一种在单个框架中独立浮动多个探针块的新型探针块组件。独立浮动探头块允许多个探头独立地对准被测器件上的相应多个匹配特征。使用单个框架允许通过一个致动运动进行多次插入探针测试。

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