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31. 发明授权

US08521990B2 Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders 有权
标题翻译：在环网中嵌入全局屏障和集体，每个节点根据类映射将接收器的输入组合到输出到发送器
公开(公告)号：US08521990B2
公开(公告)日：2013-08-27
申请号：US12723277
申请日：2010-03-12
申请人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
发明人： Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Philip Heidelberger , Robert M. Senger , Valentina Salapura , Burkhard Steinmacher-Burow , Yutaka Sugawara , Todd E. Takken
IPC分类号： G06F15/16
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
摘要翻译：本发明的实施例提供了一种用于在被组织为环面网络的并行计算机系统中嵌入全局屏障和全局中断网络的方法，系统和计算机程序产品。计算机系统包括多个节点。在一个实施例中，该方法包括从节点的一组接收器中获取输入，将来自接收器的输入划分为多个类，组合每个类的输入以获得结果，并将所述结果发送到一组的节点的发送者。本发明的实施例提供了一种用于将集体网络嵌入组织为环面网络的并行计算机系统中的方法，系统和计算机程序产品。在一个实施例中，该方法包括向环形网络添加集中逻辑以在树结构中的至少一组节点之间路由消息。

32. 发明申请

US20110173421A1 MULTI-INPUT AND BINARY REPRODUCIBLE, HIGH BANDWIDTH FLOATING POINT ADDER IN A COLLECTIVE NETWORK 有权
标题翻译：多输入和二进制可复现，集合网络中的高带宽浮点添加
公开(公告)号：US20110173421A1
公开(公告)日：2011-07-14
申请号：US12684776
申请日：2010-01-08
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
IPC分类号： G06F9/302
CPC分类号： G06F7/38 , G06F7/485 , G06F9/30014 , G06F9/30025 , G06F9/3885 , G06F2207/3808
摘要： To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.
摘要翻译：为了在并行计算系统中添加浮点数，集体逻辑器件从计算节点接收浮点数。集体逻辑器件将浮点数转换为整数。集体逻辑器件添加整数并产生整数的求和。集体逻辑设备将求和转换为浮点数。集体逻辑设备执行接收，转换浮点数，加法，生成和一次转换求和。一次通过表示计算节点仅向集体逻辑设备发送一次输入，并从集体逻辑设备接收一次输出。

33. 发明申请

US20050081078A1 Deterministic error recovery protocol 失效
标题翻译：确定性错误恢复协议
公开(公告)号：US20050081078A1
公开(公告)日：2005-04-14
申请号：US10674952
申请日：2003-09-30
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Philip Heidelberger , Dirk Hoenicke , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , H04L29/06 , H04L29/14
CPC分类号： G06F11/1443 , G06F11/0709 , G06F11/0793 , H04L1/0052 , H04L69/28 , H04L69/40 , H04L2001/0092
摘要： Disclosed are an error recovery method and system for use with a communication system having first and second nodes, each of said nodes having a receiver and a sender, the sender of the first node being connected to the receiver of the second node by a first cable, and the sender of the second node being connected to the receiver of the first node by a second cable. The method comprising the step of after one of the nodes detects an error, both of the nodes entering the same defined state. In particular, the receiver of the first node enters an error state, stays in the error state for a defined period of time T, and, after said defined period of time T, enters a wait state. Also, the sender of the first node sends to the receiver of the second node an error message for a defined period of time Te, and after the defined period of time Te, the sender of the first node enters an idle state.
摘要翻译：公开了一种用于与具有第一和第二节点的通信系统一起使用的错误恢复方法和系统，每个所述节点具有接收器和发送器，第一节点的发送器通过第一电缆连接到第二节点的接收器并且第二节点的发送者通过第二电缆连接到第一节点的接收器。所述方法包括在所述节点中的一个检测到错误之后的两个节点进入相同的定义状态的步骤。特别地，第一节点的接收机进入错误状态，在定义的时间段T内保持在错误状态，并且在所述定义的时间段T之后进入等待状态。此外，第一节点的发送方在给定的时间段Te的情况下向第二节点的接收者发送错误消息，并且在定义的时间段Te之后，第一节点的发送者进入空闲状态。

34. 发明申请

US20060224837A1 Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture 有权
公开(公告)号：US20060224837A1
公开(公告)日：2006-10-05
申请号：US11093131
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/084 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

35. 发明申请

US20060224838A1 Novel snoop filter for filtering snoop requests 有权
标题翻译：用于过滤窥探请求的新型窥探过滤器
公开(公告)号：US20060224838A1
公开(公告)日：2006-10-05
申请号：US11093152
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与其可操作地相连的一个或多个本地高速缓冲存储器。该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求写入源并将这些请求的子集转发到其相关联的处理单元。

36. 发明申请

US20060224835A1 Snoop filtering system in a multiprocessor system 有权
标题翻译：多处理器系统中的Snoop过滤系统
公开(公告)号：US20060224835A1
公开(公告)日：2006-10-05
申请号：US11093127
申请日：2005-03-29
申请人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
发明人： Matthias Blumrich , Dong Chen , Alan Gara , Mark Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813 , Y02D10/13
摘要： A system and method for supporting cache coherency in a computing environment having multiple processing units, each unit having an associated cache memory system operatively coupled therewith. The system includes a plurality of interconnected snoop filter units, each snoop filter unit corresponding to and in communication with a respective processing unit, with each snoop filter unit comprising a plurality of devices for receiving asynchronous snoop requests from respective memory writing sources in the computing environment; and a point-to-point interconnect comprising communication links for directly connecting memory writing sources to corresponding receiving devices; and, a plurality of parallel operating filter devices coupled in one-to-one correspondence with each receiving device for processing snoop requests received thereat and one of forwarding requests or preventing forwarding of requests to its associated processing unit. Each of the plurality of parallel operating filter devices comprises parallel operating sub-filter elements, each simultaneously receiving an identical snoop request and implementing one or more different snoop filter algorithms for determining those snoop requests for data that are determined not cached locally at the associated processing unit and preventing forwarding of those requests to the processor unit. In this manner, a number of snoop requests forwarded to a processing unit is reduced thereby increasing performance of the computing environment.
摘要翻译：一种用于在具有多个处理单元的计算环境中支持高速缓存一致性的系统和方法，每个单元具有与其可操作耦合的相关联的高速缓存存储器系统该系统包括多个互连的窥探过滤器单元，每个窥探过滤器单元对应于相应处理单元并与其通信，每个窥探过滤器单元包括用于在计算环境中从相应存储器写入源接收异步窥探请求的多个设备 ; 以及包括用于将存储器写入源直接连接到对应的接收设备的通信链路的点对点互连; 以及与每个接收设备一一对应地耦合的多个并行操作过滤器设备，用于处理在其上接收的窥探请求，并且转发请求之一或者阻止将请求转发到其相关联的处理单元。多个并行操作过滤器装置中的每一个包括并行操作子滤波器元件，每个并行操作子滤波器元件同时接收相同的窥探请求，并且实现一个或多个不同的窥探滤波器算法，用于确定对于在相关处理中本地未被缓存的数据被确定的窥探请求并且防止将这些请求转发到处理器单元。以这种方式，减少了转发到处理单元的多个窥探请求，从而增加了计算环境的性能。

37. 发明授权

US09037669B2 Remote processing and memory utilization 有权
标题翻译：远程处理和内存利用
公开(公告)号：US09037669B2
公开(公告)日：2015-05-19
申请号：US13570916
申请日：2012-08-09
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , James A. Kahle , Fabrizio Petrini , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F15/167 , G06F15/173 , G06F11/00 , G06F9/54 , H04L29/06
CPC分类号： G06F9/547 , H04L29/0617 , H04L67/40
摘要： According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
摘要翻译：根据本发明的一个实施例，一种用于操作存储器的系统包括由网络耦合到第二节点的第一节点，所述系统被配置为执行一种方法，该方法包括从所述第二节点接收来自所述第二节点的处理元件中的所述远程事务消息第一节点经由网络，其中当所述远程事务消息被传送到所述处理元件时，所述远程事务消息绕过所述第一节点中的主处理器。此外，该方法包括基于远程事务消息，由处理元件访问来自第一节点中的存储器中的位置的数据，以及由处理元件基于数据和远程事务消息执行计算。

38. 发明授权

US08977669B2 Multi-input and binary reproducible, high bandwidth floating point adder in a collective network 有权
标题翻译：集成网络中的多输入和二进制可重复的高带宽浮点加法器
公开(公告)号：US08977669B2
公开(公告)日：2015-03-10
申请号：US12684776
申请日：2010-01-08
申请人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
发明人： Dong Chen , Noel A. Eisley , Philip Heidelberger , Burkhard Steinmacher-Burow
IPC分类号： G06F7/38 , G06F9/30 , G06F9/38
CPC分类号： G06F7/38 , G06F7/485 , G06F9/30014 , G06F9/30025 , G06F9/3885 , G06F2207/3808
摘要： To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.
摘要翻译：为了在并行计算系统中添加浮点数，集体逻辑器件从计算节点接收浮点数。集体逻辑器件将浮点数转换为整数。集体逻辑器件添加整数并产生整数的求和。集体逻辑设备将求和转换为浮点数。集体逻辑设备执行接收，转换浮点数，加法，生成和一次转换求和。一次通过表示计算节点仅向集体逻辑设备发送一次输入，并从集体逻辑设备接收一次输出。

39. 发明申请

US20110219188A1 CACHE AS POINT OF COHERENCE IN MULTIPROCESSOR SYSTEM 有权
标题翻译： CACHE作为多处理器系统中的一致性点
公开(公告)号：US20110219188A1
公开(公告)日：2011-09-08
申请号：US13008531
申请日：2011-01-18
申请人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmarcht , Burkhard Steinmacher-Burow , Zhuang Xiaotong
发明人： Matthias A. Blumrich , Luis H. Ceze , Dong Chen , Alan Gara , Philip Heidelberger , Martin Ohmarcht , Burkhard Steinmacher-Burow , Zhuang Xiaotong
IPC分类号： G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.
摘要翻译：在多处理器系统中，在L2高速缓冲存储器中实现冲突检查机制。不同版本的推测性写入以不同的方式保存在缓存中。高速缓存目录中保留了推测性写入记录。冲突检查作为目录查找的一部分发生。不冲突的推测版本以不同的缓存方式聚合成聚合版本。推测内存访问请求不会转到主内存。

40. 发明授权

US07802025B2 DMA engine for repeating communication patterns 失效
标题翻译：用于重复通信模式的DMA引擎
公开(公告)号：US07802025B2
公开(公告)日：2010-09-21
申请号：US11768795
申请日：2007-06-26
申请人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F13/28
CPC分类号： G06F15/163
摘要： A parallel computer system is constructed as a network of interconnected compute nodes to operate a global message-passing application for performing communications across the network. Each of the compute nodes includes one or more individual processors with memories which run local instances of the global message-passing application operating at each compute node to carry out local processing operations independent of processing operations carried out at other compute nodes. Each compute node also includes a DMA engine constructed to interact with the application via Injection FIFO Metadata describing multiple Injection FIFOs where each Injection FIFO may containing an arbitrary number of message descriptors in order to process messages with a fixed processing overhead irrespective of the number of message descriptors included in the Injection FIFO.
摘要翻译：并行计算机系统被构造为互连的计算节点的网络，以操作用于在整个网络上执行通信的全局消息传递应用。每个计算节点包括具有存储器的一个或多个单独处理器，该存储器运行在每个计算节点处操作的全局消息传递应用的本地实例，以独立于在其他计算节点执行的处理操作来执行本地处理操作。每个计算节点还包括构造成通过描述多个注入FIFO的注入FIFO元数据与应用交互的DMA引擎，其中每个注入FIFO可以包含任意数量的消息描述符，以便处理具有固定处理开销的消息，而不管消息的数量描述符包含在注入FIFO中。

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