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31. 发明申请

US20070113044A1 Method and Apparatus for Preloading Translation Buffers 失效
标题翻译：预处理缓冲器的方法和装置
公开(公告)号：US20070113044A1
公开(公告)日：2007-05-17
申请号：US11621315
申请日：2007-01-09
申请人： Michael Day , Jonathan DeMent , Charles Johns
发明人： Michael Day , Jonathan DeMent , Charles Johns
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/654 , G06F2212/684
摘要： A method and an apparatus are provided for efficiently managing the operation of a translation buffer. A software and hardware apparatus and method are utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache. A software pre-load mechanism may be provided for preloading a translation lookaside buffer (TLB) via a hardware implemented controller. Following preloading of the TLB, control of accessing the TLB may be handed over to the hardware implemented controller. Upon an application context switch operation, the software preload mechanism may be utilized again to preload the TLB with new translation information for the newly active application instance.
摘要翻译：提供了一种用于有效地管理翻译缓冲器的操作的方法和装置。使用软件和硬件装置和方法来预加载翻译缓冲器，以防止由于缓存缓慢升温而造成的不良操作。可以提供软件预加载机制，用于经由硬件实现的控制器来预加载翻译后备缓冲器（TLB）。在TLB的预加载之后，可以将访问TLB的控制权交给硬件实现的控制器。在应用程序上下文切换操作时，可以再次利用软件预载机制来为新活动的应用实例的新的翻译信息预加载TLB。

32. 发明申请

US20070087292A1 Color forming compositions 审中-公开
标题翻译：成色组合物
公开(公告)号：US20070087292A1
公开(公告)日：2007-04-19
申请号：US11250268
申请日：2005-10-13
申请人： Michael Day , Makarand Gore , Jayprakash Bhatt
发明人： Michael Day , Makarand Gore , Jayprakash Bhatt
IPC分类号： B41M5/20
CPC分类号： B41M5/30 , B41M5/323 , B41M5/3333 , B41M5/465
摘要： A color forming composition is provided herein. According to one exemplary embodiment, a color forming composition includes a polymer matrix; an aromatic sulfonylurea activator, a radiation absorber, and an isobenzofuranone color former dye.
摘要翻译：本发明提供一种成色组合物。根据一个示例性实施方案，成色组合物包含聚合物基质; 芳族磺酰脲活化剂，辐射吸收剂和异苯并呋喃酮着色染料。

33. 发明申请

US20070079018A1 System and method for communicating command parameters between a processor and a memory flow controller 失效
标题翻译：用于在处理器和存储器流控制器之间传送命令参数的系统和方法
公开(公告)号：US20070079018A1
公开(公告)日：2007-04-05
申请号：US11207986
申请日：2005-08-19
申请人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
发明人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
IPC分类号： G06F13/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

34. 发明申请

US20070043936A1 System and method for communicating with a processor event facility 失效
标题翻译：与处理器事件设施通信的系统和方法
公开(公告)号：US20070043936A1
公开(公告)日：2007-02-22
申请号：US11207971
申请日：2005-08-19
申请人： Michael Day , Charles Johns , John Liberty , Todd Swanson
发明人： Michael Day , Charles Johns , John Liberty , Todd Swanson
IPC分类号： G06F7/38
CPC分类号： G06F13/24
摘要： A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于与处理器事件设施进行通信的系统和方法。系统和方法利用通道接口作为与处理器事件设施通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

35. 发明申请

US20060269813A1 Supported ceramic membranes and electrochemical cells and cell stacks including the same 失效
标题翻译：支持的陶瓷膜和电化学电池和电池堆包括它们
公开(公告)号：US20060269813A1
公开(公告)日：2006-11-30
申请号：US11141259
申请日：2005-05-31
申请人： Matthew Seabaugh , Katarzyna Sabolsky , Edward Sabolsky , Michael Day
发明人： Matthew Seabaugh , Katarzyna Sabolsky , Edward Sabolsky , Michael Day
IPC分类号： H01M8/12 , C04B35/64 , H01M4/88 , B05D5/12
CPC分类号： H01M8/1226 , B01D67/0041 , B01D69/02 , B01D69/12 , B01D69/125 , B01D71/024 , B01D2325/02 , C04B38/0675 , C04B38/068 , C04B2111/00612 , C04B2111/00801 , C04B2111/00853 , H01M8/124 , H01M8/1253 , H01M2008/1293 , H01M2300/0094 , Y02E60/525 , Y02P70/56 , C04B35/48 , C04B38/0054 , C04B38/0074
摘要： A dense ceramic electrolyte membrane supported by symmetrical porous ceramic electrolyte layers. The thin (t
摘要翻译：由对称多孔陶瓷电解质层支撑的致密陶瓷电解质膜。薄（t <100微米）电解质层被夹在两个在烧成后变得高度多孔的含有逸散剂的电解质支撑层。经热处理的含挥发物的载体层形成具有强电解质的骨架结构，其具有总是从电解质表面延伸的孔的互穿网络。多孔层可以用一系列电极材料或前体渗透以形成固体氧化物燃料电池或其它电化学电池以及电化学电池组。与常规结构相比，支撑的陶瓷膜提供电化学性能优点并减少烧结过程中的翘曲。

36. 发明申请

US20060245119A1 Memory module with a predetermined arrangement of pins 有权
公开(公告)号：US20060245119A1
公开(公告)日：2006-11-02
申请号：US11108245
申请日：2005-04-18
申请人： June Goodwin , Michael Day , Brian Johnson , John Nerl , Richard Schumacher , Vicki Smith
发明人： June Goodwin , Michael Day , Brian Johnson , John Nerl , Richard Schumacher , Vicki Smith
IPC分类号： H02H7/00
CPC分类号： G11C5/14 , G11C5/04 , H05K1/0219 , H05K1/0231 , H05K1/0263 , H05K1/117 , H05K2201/09145
摘要： A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

37. 发明申请

US20060234100A1 Self-supporting ceramic membranes and electrochemical cells and cell stacks including the same 有权
标题翻译：自支撑陶瓷膜和电化学电池和电池堆包括它们
公开(公告)号：US20060234100A1
公开(公告)日：2006-10-19
申请号：US11109471
申请日：2005-04-19
申请人： Michael Day , Katarzyna Sabolsky , Todd Lesousky , Matthew Seabaugh
发明人： Michael Day , Katarzyna Sabolsky , Todd Lesousky , Matthew Seabaugh
IPC分类号： H01M8/12 , H01M4/90 , B05D5/12 , H01M4/88
CPC分类号： B01D67/0041 , B01D69/06 , B01D69/10 , B01D71/024 , B01D2325/08 , B01D2325/26 , C01B13/0255 , H01M4/8828 , H01M4/8839 , H01M4/8889 , H01M4/9033 , H01M4/9066 , H01M8/1226 , H01M8/1253 , H01M2300/0077 , H01M2300/0094 , Y02E60/525 , Y02P70/56
摘要： Self-supporting thin film membranes of ceramic materials and related electrochemical cells and cell stacks. The membrane structure is divided into a plurality of self-supporting thin membrane regions by a network of thicker integrated support ribs. The membrane structure may be prepared by laminating a thin electrolyte layer with a thicker ceramic layer that forms a network of support ribs.
摘要翻译：陶瓷材料的自支撑薄膜和相关的电化学电池和电池堆。膜结构通过较厚的整体支撑肋的网络被分成多个自支撑薄膜区域。膜结构可以通过层叠具有形成支撑肋网络的较厚陶瓷层的薄电解质层来制备。

38. 发明申请

US20060166035A1 Thermally crosslinkable materials and multi-layered devices therefrom 有权
标题翻译：热交联材料及其多层装置
公开(公告)号：US20060166035A1
公开(公告)日：2006-07-27
申请号：US10534087
申请日：2003-11-07
申请人： Yuning Li , Jianfu Ding , Michael Day , Ye Tao , Marie D'Iorio
发明人： Yuning Li , Jianfu Ding , Michael Day , Ye Tao , Marie D'Iorio
IPC分类号： B32B19/00
CPC分类号： H05B33/14 , C09K11/06 , C09K2211/1416 , C09K2211/1425 , C09K2211/1433 , C09K2211/1466 , H01L51/0039 , H01L51/0072 , H01L51/0079 , H01L51/008 , H01L51/0081 , H01L51/5012 , H01L51/5048 , Y10S428/917
摘要： The invention disclosed relates to cross-linkable composites of boronic acid or a boronic acid derivative such as a boronate, and an organic or organo-metallic moiety having a functionality such as hole transporting, electron transporting and light emitting, to cross-linked composites and to methods for making same. Multi-layer materials and optoelectronic devices including such cross-linked composites are also disclosed.
摘要翻译：所公开的发明涉及硼酸或硼酸衍生物如硼酸酯和具有诸如空穴传输，电子传输和发光的官能团的有机或有机金属部分与交联的复合材料的交联复合物，以及制作相同的方法。还公开了包括这种交联复合材料的多层材料和光电子器件。

39. 发明申请

US20060070069A1 System and method for sharing resources between real-time and virtualizing operating systems 审中-公开
标题翻译：在实时和虚拟化操作系统之间共享资源的系统和方法
公开(公告)号：US20060070069A1
公开(公告)日：2006-03-30
申请号：US10955184
申请日：2004-09-30
申请人： Maximino Aguilar , Michael Day , Mark Nutter , James Xenidis
发明人： Maximino Aguilar , Michael Day , Mark Nutter , James Xenidis
IPC分类号： G06F9/46
CPC分类号： G06F9/5016 , G06F9/544
摘要： A system and method for sharing resources between real-time and virtualizing operating systems is presented. A computer system uses effective address mapping of support processors' local memory to share resources between separate operating systems. When threads are created for either operating system, the thread's corresponding processor memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by the thread, regardless of whether the processor is running, or whether the processor is executing a different thread from a different operating system. For example, a computer system may have eight support processors and running two operating systems whereby the first operating system requires six support processors and the second operating system requires all eight support processors. In this example, resources are virtualized and shared between the two operating systems in order to meet the requirements of both operating systems.
摘要翻译：介绍了一种在实时和虚拟化操作系统之间共享资源的系统和方法。计算机系统使用支持处理器的本地存储器的有效地址映射来在不同的操作系统之间共享资源。当为任一操作系统创建线程时，线程的相应处理器内存映射到有效的地址空间。在这样做时，处理器的本地内存可由线程访问，无论处理器是否在运行，还是处理器是否正在从不同的操作系统执行不同的线程。例如，计算机系统可以具有八个支持处理器并且运行两个操作系统，由此第一操作系统需要六个支持处理器，而第二操作系统需要所有八个支持处理器。在这个例子中，为了满足两个操作系统的要求，在两个操作系统之间虚拟化和共享资源。

40. 发明申请

US20060026309A1 Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
标题翻译：非对称异构多处理器环境中的内存障碍原语
公开(公告)号：US20060026309A1
公开(公告)日：2006-02-02
申请号：US10902474
申请日：2004-07-29
申请人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.
摘要翻译：本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。接收到存储器屏障命令并接收存储器命令。内存命令是根据内存屏障命令执行的。基于内存障碍命令启动总线操作。基于总线操作接收总线操作确认。基于总线操作确认执行存储器障碍命令。在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

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