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1. 发明申请

US20050160229A1 Method and apparatus for preloading translation buffers 审中-公开
标题翻译：用于预加载翻译缓冲区的方法和装置
公开(公告)号：US20050160229A1
公开(公告)日：2005-07-21
申请号：US10759941
申请日：2004-01-16
申请人： Charles Johns , Michael Day , Jonathan DeMent
发明人： Charles Johns , Michael Day , Jonathan DeMent
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1027 , G06F2212/654 , G06F2212/684
摘要： A method and an apparatus are provided for efficiently managing the operation of a translation buffer. A software and hardware apparatus and method are utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache.
摘要翻译：提供了一种用于有效地管理翻译缓冲器的操作的方法和装置。使用软件和硬件装置和方法来预加载翻译缓冲器，以防止由于缓存缓慢升温而造成的不良操作。

2. 发明申请

US20070113044A1 Method and Apparatus for Preloading Translation Buffers 失效
标题翻译：预处理缓冲器的方法和装置
公开(公告)号：US20070113044A1
公开(公告)日：2007-05-17
申请号：US11621315
申请日：2007-01-09
申请人： Michael Day , Jonathan DeMent , Charles Johns
发明人： Michael Day , Jonathan DeMent , Charles Johns
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/654 , G06F2212/684
摘要： A method and an apparatus are provided for efficiently managing the operation of a translation buffer. A software and hardware apparatus and method are utilized to pre-load a translation buffer to prevent poor operation as a result of slow warming of a cache. A software pre-load mechanism may be provided for preloading a translation lookaside buffer (TLB) via a hardware implemented controller. Following preloading of the TLB, control of accessing the TLB may be handed over to the hardware implemented controller. Upon an application context switch operation, the software preload mechanism may be utilized again to preload the TLB with new translation information for the newly active application instance.
摘要翻译：提供了一种用于有效地管理翻译缓冲器的操作的方法和装置。使用软件和硬件装置和方法来预加载翻译缓冲器，以防止由于缓存缓慢升温而造成的不良操作。可以提供软件预加载机制，用于经由硬件实现的控制器来预加载翻译后备缓冲器（TLB）。在TLB的预加载之后，可以将访问TLB的控制权交给硬件实现的控制器。在应用程序上下文切换操作时，可以再次利用软件预载机制来为新活动的应用实例的新的翻译信息预加载TLB。

3. 发明申请

US20070088866A1 Destructive DMA lists 失效
标题翻译：破坏性DMA列表
公开(公告)号：US20070088866A1
公开(公告)日：2007-04-19
申请号：US11252532
申请日：2005-10-18
申请人： Michael Day , Charles Johns , Barry Minor
发明人： Michael Day , Charles Johns , Barry Minor
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A buffer, a method, and a computer program product for DMA transfers are provided that are designed to save memory space within a local memory of a processor. The buffer is a return buffer with a portion reserved for DMA lists. A DMA controller accomplishes DMA transfers by: reading address elements from a DMA list located in the DMA list portion; reading the corresponding data from system memory; and copying the corresponding data to the return buffer portion. This buffer saves space because when the buffer begins to fill up the corresponding return data can overwrite the data in the DMA list. Accordingly, the DMA list overlays on top of the return buffer, such that the return data can destruct the DMA list and the extra storage space for the DMA list is saved.
摘要翻译：提供了用于DMA传输的缓冲器，方法和计算机程序产品，其被设计为在处理器的本地存储器内节省存储器空间。缓冲区是具有为DMA列表保留的部分的返回缓冲区。 DMA控制器通过以下方式完成DMA传输：从位于DMA列表部分的DMA列表读取地址元素; 从系统内存读取相应的数据; 并将相应的数据复制到返回缓冲器部分。此缓冲区可节省空间，因为当缓冲区开始填满相应的返回数据时，可以覆盖DMA列表中的数据。因此，DMA列表覆盖在返回缓冲器的顶部，使得返回数据可以破坏DMA列表，并且保存DMA列表的额外的存储空间。

4. 发明申请

US20070016733A1 Method to Provide Atomic Update Primitives in an Asymmetric Heterogeneous Multiprocessor Environment 有权
标题翻译：在非对称异构多处理器环境中提供原子更新原语的方法
公开(公告)号：US20070016733A1
公开(公告)日：2007-01-18
申请号：US11468317
申请日：2006-08-30
申请人： Michael Day , Charles Johns , James Kahle , Peichum Liu , Thuong Truong
发明人： Michael Day , Charles Johns , James Kahle , Peichum Liu , Thuong Truong
IPC分类号： G06F12/14 , G06F13/28
CPC分类号： G06F13/28 , G06F9/3004 , G06F9/30087 , G06F12/0831 , G06F2213/0038
摘要： The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.
摘要翻译：本发明提供了具有具有DMA传输的共享存储器的非对称单芯片异构多处理器计算机系统中的原子更新原语。从包括具有预留的get lock line命令，put lock line条件命令和put lock line无条件命令的集合中生成至少一个lock line命令。

5. 发明申请

US20060095668A1 Method for processor to use locking cache as part of system memory 失效
标题翻译：处理器使用锁定缓存作为系统内存的一部分的方法
公开(公告)号：US20060095668A1
公开(公告)日：2006-05-04
申请号：US10976260
申请日：2004-10-28
申请人： Michael Day , Charles Johns , Thuong Truong
发明人： Michael Day , Charles Johns , Thuong Truong
IPC分类号： G06F12/14
CPC分类号： G06F12/126 , G06F12/0848 , G06F2212/2515
摘要： The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.
摘要翻译：本发明提供了一种用于处理器将数据写入高速缓存或其他快速存储器的方法，而不将其写入主存储器。此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。数据保留在锁定缓存中，直到它在软件控制下被特别覆盖为止。锁定缓存或其他快速存储器可用作附加系统内存。在本发明的实施例中，锁定高速缓存是多组关联高速缓存的一组或多组方式，但不是所有的集合或方式。

6. 发明申请

US20050111478A1 Distributed control load shaping method and apparatus 审中-公开
标题翻译：分布式控制负载整形方法及装置
公开(公告)号：US20050111478A1
公开(公告)日：2005-05-26
申请号：US10718936
申请日：2003-11-20
申请人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
发明人： Jeffrey Brown , Michael Day , Charles Johns , Thuong Truong , Takeshi Yamazaki
IPC分类号： H04L12/56 , H04L12/42
CPC分类号： H04L47/822 , H04L47/13 , H04L47/20 , H04L47/22 , H04L47/2441 , H04L47/39 , H04L47/70 , H04L47/72 , H04L47/781 , H04L47/803 , H04L47/821
摘要： Disclosed is an apparatus for controlling or managing the transmission of data packets over a multiplexed communication path, referred to herein as a bus, on a priority basis up to a given authorized BW (Bandwidth), in a given operational time period, for presently authorized devices or applications. Non-managed (not presently authorized) bus requests are handled in a prior art “best effort” basis.
摘要翻译：公开了一种用于在给定的操作时间段内，在给定的操作时间段内优先地基于多路通信路径（这里称为总线）来控制或管理数据分组的传输的装置，用于当前授权的设备或应用程序。非管理（未授权）总线请求以现有技术“尽力而为”为基础来处理。

7. 发明申请

US20050055505A1 Software-controlled cache set management with software-generated class identifiers 失效
标题翻译：软件控制的缓存集管理与软件生成的类标识符
公开(公告)号：US20050055505A1
公开(公告)日：2005-03-10
申请号：US10655365
申请日：2003-09-04
申请人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Harm Hofstee , Charles Johns , James Kahle , David Shippy , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126
摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.
摘要翻译：本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。根据地址未命中创建类标识符。替换管理表可用于读取类标识符以创建标签替换控制标记。包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

8. 发明申请

US20070079018A1 System and method for communicating command parameters between a processor and a memory flow controller 失效
标题翻译：用于在处理器和存储器流控制器之间传送命令参数的系统和方法
公开(公告)号：US20070079018A1
公开(公告)日：2007-04-05
申请号：US11207986
申请日：2005-08-19
申请人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
发明人： Michael Day , Charles Johns , Peichun Liu , Todd Swanson , Thuong Truong
IPC分类号： G06F13/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统和方法。系统和方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

9. 发明申请

US20070043936A1 System and method for communicating with a processor event facility 失效
标题翻译：与处理器事件设施通信的系统和方法
公开(公告)号：US20070043936A1
公开(公告)日：2007-02-22
申请号：US11207971
申请日：2005-08-19
申请人： Michael Day , Charles Johns , John Liberty , Todd Swanson
发明人： Michael Day , Charles Johns , John Liberty , Todd Swanson
IPC分类号： G06F7/38
CPC分类号： G06F13/24
摘要： A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于与处理器事件设施进行通信的系统和方法。系统和方法利用通道接口作为与处理器事件设施通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

10. 发明申请

US20060026309A1 Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment 有权
标题翻译：非对称异构多处理器环境中的内存障碍原语
公开(公告)号：US20060026309A1
公开(公告)日：2006-02-02
申请号：US10902474
申请日：2004-07-29
申请人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
发明人： Michael Day , Charles Johns , Peichun Liu , Thuong Truong , Takeshi Yamazaki
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.
摘要翻译：本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。接收到存储器屏障命令并接收存储器命令。内存命令是根据内存屏障命令执行的。基于内存障碍命令启动总线操作。基于总线操作接收总线操作确认。基于总线操作确认执行存储器障碍命令。在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

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