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1. 发明申请

US20050289440A1 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US20050289440A1
公开(公告)日：2005-12-29
申请号：US10879262
申请日：2004-06-29
申请人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption to detect a repeated bit pattern of data corruption across different addresses of the memory subsystem, and code for controlling application of the ECC algorithm to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
摘要翻译：在本发明的一个实施例中，包括用于控制存储器子系统中的纠错码（ECC）算法的应用的可执行指令的计算机可读介质包括用于记录从存储器子系统检索的数据中的数据损坏的发生的代码，分析数据损坏的发生以检测在存储器子系统的不同地址之间的数据损坏的重复位模式;以及用于控制ECC算法的应用以擦除与由用于分析的代码检测的重复位模式相关联的位的代码，从内存子系统检索的数据。

2. 发明申请

US20060209613A1 Memory modules and methods 失效
标题翻译：内存模块和方法
公开(公告)号：US20060209613A1
公开(公告)日：2006-09-21
申请号：US11085693
申请日：2005-03-21
申请人： Brian Johnson , John Nerl , Ronald Bellomlo , Michael Day , Vicki Smith , Richard Schumacher , Rajakrishnan Radjassamy , June Goodwin
发明人： Brian Johnson , John Nerl , Ronald Bellomlo , Michael Day , Vicki Smith , Richard Schumacher , Rajakrishnan Radjassamy , June Goodwin
IPC分类号： G11C8/00
CPC分类号： G11C5/04 , H05K1/181
摘要： Embodiments of memory modules and corresponding methods are disclosed. One memory module embodiment includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.
摘要翻译：公开了存储器模块和相应方法的实施例。一个存储器模块实施例包括印刷电路板，其包括上行存储器集成电路，下行存储器集成电路，以及第一寻址寄存器和第二寻址寄存器，第一寻址寄存器和第二寻址寄存器，每个至少具有主要提供在第一层中的地址和控制输入路由之一，第一寻址寄存器耦合到上行存储器集成电路，第二寻址寄存器耦合到下行存储器集成电路。

3. 发明授权

US07212424B2 Double-high DIMM with dual registers and related methods 失效
标题翻译：双高DIMM双重寄存器和相关方法
公开(公告)号：US07212424B2
公开(公告)日：2007-05-01
申请号：US11085693
申请日：2005-03-21
申请人： Brian M. Johnson , John Nerl , Ronald J. Bellomlo , Michael C. Day , Vicki L. Smith , Richard A. Schumacher , Rajakrishnan Radjassamy , June E. Goodwin
发明人： Brian M. Johnson , John Nerl , Ronald J. Bellomlo , Michael C. Day , Vicki L. Smith , Richard A. Schumacher , Rajakrishnan Radjassamy , June E. Goodwin
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , H05K1/181
摘要： One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.
摘要翻译：一个存储器模块包括印刷电路板，其包括上行的存储器集成电路，下一排存储器集成电路，以及第一寻址寄存器和第二寻址寄存器，第一寻址寄存器和第二寻址寄存器，每个具有至少一个主要提供在第一层中的地址和控制输入路由，第一寻址寄存器耦合到上行存储器集成电路，第二寻址寄存器耦合到下行存储器集成电路。

4. 发明申请

US20050289439A1 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US20050289439A1
公开(公告)日：2005-12-29
申请号：US10879255
申请日：2004-06-29
申请人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
摘要翻译：在一个实施例中，计算机可读介质包括用于在从存储器子系统检索的数据中记录数据损坏的发生的代码，用于确定存储器子系统内的位位置是否与多次数据损坏相关联的代码，以及响应于用于确定的代码，包含与多次数据损坏相关联的位位置的存储器区域，用于分析在存储器子系统的多个地址上重复的数据损坏模式的代码，以及用于控制由所述存储器子系统的多个地址应用纠错码（ECC）算法的代码存储器子系统从从存储器子系统检索的数据中擦除与用于分析的代码检测的重复位模式相关联的位。

5. 发明申请

US20050289402A1 System and method for applying error correction code (ECC) erasure mode and clearing recorded information from a page deallocation table 有权
标题翻译：用于应用纠错码（ECC）擦除模式的系统和方法，并从页面解除分配表中清除记录的信息
公开(公告)号：US20050289402A1
公开(公告)日：2005-12-29
申请号：US10879643
申请日：2004-06-29
申请人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1064
摘要： In one embodiment, a system comprises non-volatile memory storing a page deallocation table (PDT), a memory controller for storing and retrieving data from a memory subsystem, the memory controller using an error correction code (ECC) algorithm to correct data corruption in retrieved data, a processor for executing an error analysis algorithm, the error analysis algorithm recording instances of data corruption in the PDT, deallocating memory regions associated with multiple occurrences of data corruption at single bit locations, the error analysis algorithm causing the memory controller to apply an erasure mode of the ECC algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removing entries in the PDT that correspond to data corruption addressed by application of the erasure mode.
摘要翻译：在一个实施例中，系统包括存储页面解除分配表（PDT）的非易失性存储器，用于从存储器子系统存储和检索数据的存储器控制器，存储器控制器使用纠错码（ECC）算法来校正数据损坏检索数据，用于执行错误分析算法的处理器，记录PDT中的数据损坏实例的错误分析算法，在单个位置释放与多次数据损坏相关联的存储器区域，使得存储器控制器应用的误差分析算法 ECC算法的擦除模式，当检测到在存储器子系统的不同地址上重复的数据损坏模式时，以及删除对应于通过应用擦除模式解决的数据损坏的PDT中的条目。

6. 发明申请

US20060245119A1 Memory module with a predetermined arrangement of pins 有权
公开(公告)号：US20060245119A1
公开(公告)日：2006-11-02
申请号：US11108245
申请日：2005-04-18
申请人： June Goodwin , Michael Day , Brian Johnson , John Nerl , Richard Schumacher , Vicki Smith
发明人： June Goodwin , Michael Day , Brian Johnson , John Nerl , Richard Schumacher , Vicki Smith
IPC分类号： H02H7/00
CPC分类号： G11C5/14 , G11C5/04 , H05K1/0219 , H05K1/0231 , H05K1/0263 , H05K1/117 , H05K2201/09145
摘要： A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

7. 发明授权

US06591372B1 Zero clock skew computer module 失效
标题翻译：零时钟偏移计算机模块
公开(公告)号：US06591372B1
公开(公告)日：2003-07-08
申请号：US09392599
申请日：1999-09-09
申请人： John Nerl
发明人： John Nerl
IPC分类号： G06F110
CPC分类号： G06F1/10
摘要： The length of the phase lock feedback path of the phase lock loop chip (PLL chip) is adjusted so that the timing of clock pulses at computer chips is measured relative to the arrival time of a clock pulse at the computer board clock pin. This adjustment of the length of the phase lock loop accounts for the length of the trace from the computer board clock pin to the PLL clock input pin. This adjustment of the length of the phase lock loop removes uncertainty between vendors in the arrival time of clock pulses at the computer chips, relative to arrival time of clock pulses at the computer board clock pin. A system designer then has control of the arrival time of a pulse at a computer chip clock pin by adjustment of the arrival time of the clock pulse at the computer board clock pin, and no variation is introduced between vendors who adopt the invention in their design of computer boards.
摘要翻译：调整锁相环芯片（PLL芯片）的锁相反馈路径的长度，以便相对于计算机板时钟引脚上的时钟脉冲的到达时间测量计算机芯片的时钟脉冲定时。锁相环长度的这种调整是从电脑板时钟引脚到PLL时钟输入引脚的走线长度。相对于计算机板时钟引脚上的时钟脉冲的到达时间，锁相环长度的这种调整在计算机芯片上的时钟脉冲到达时间消除了供应商之间的不确定性。然后，系统设计者通过调整计算机板时钟引脚上的时钟脉冲的到达时间来控制脉冲到计算机芯片时钟引脚的到达时间，并且在其设计中采用本发明的供应商之间没有引入变化的电脑板。

8. 发明授权

US6043987A Printed circuit board having a well structure accommodating one or more capacitor components 失效
标题翻译：具有容纳一个或多个电容器部件的阱结构的印刷电路板
公开(公告)号：US6043987A
公开(公告)日：2000-03-28
申请号：US918248
申请日：1997-08-25
申请人： Paul M. Goodwin , John Nerl
发明人： Paul M. Goodwin , John Nerl
IPC分类号： H05K1/18
CPC分类号： H05K1/183
摘要： Printed Circuit Board fabrication costs are decreased, and device placement densities are increased by the use of well structures designed for receiving components such as capacitors on portions of the PCB directly beneath integrated circuit packages having very low vertical profiles. With such an arrangement it is possible to use newer low profile packages and still place a capacitor under the integrated circuit package for reduced area consumption and improved inductance and circuit cycle times. Further advantages of the present arrangement include a reduction in the number of vias that need to be drilled in the PCB to make capacitor attachments, a consequent improvement in PCB inductance and parasitic capacitance, and improved electrical properties for voltage reference planes and routing layers.
摘要翻译：印刷电路板制造成本降低，并且通过使用设计用于在具有非常低的垂直轮廓的集成电路封装下方的PCB的部分上接收诸如电容器的部件的阱结构来增加器件放置密度。通过这样的布置，可以使用较新的薄型封装，并且还将电容器放置在集成电路封装下，以减少面积消耗，并改善电感和电路循环时间。本发明的另外的优点包括减少在PCB中需要钻孔以形成电容器附件的通孔的数量，随之而来的PCB电感和寄生电容的改善以及电压参考平面和布线层的改善的电性能。

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