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31. 发明授权

US07932566B2 Structure and system of mixing poly pitch cell design under default poly pitch design rules 有权
标题翻译：在默认聚沥青设计规则下混合聚沥青单元设计的结构和系统
公开(公告)号：US07932566B2
公开(公告)日：2011-04-26
申请号：US12347628
申请日：2008-12-31
申请人： Yung-Chin Hou , Li-Chun Tien , Lee-Chung Lu , Ping Chung Li , Ta-Pen Guo
发明人： Yung-Chin Hou , Li-Chun Tien , Lee-Chung Lu , Ping Chung Li , Ta-Pen Guo
IPC分类号： H01L25/00
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11803
摘要： An integrated circuit including type-1 cells and a type-2 cell is presented. The type-1 cells have poly lines with a default poly pitch. The type-2 cell has poly lines with a non-default poly pitch. A first boundary region has at least one isolation area that lies between the type-1 cells and the type-2 cell in the X-direction. The first boundary region includes at least one merged dummy poly line, wherein the at least one merged dummy poly line has a first portion that complies with the default poly pitch of the type-1 cells and a second portion that complies with the non-default poly pitch of the type-2 cell.
摘要翻译：提出了包括1型电池和2型电池的集成电路。 1型电池具有默认聚间距的多线。 2型电池具有具有非默认聚间距的多线。第一边界区域具有位于X方向上的类型1单元和类型2单元之间的至少一个隔离区域。第一边界区域包括至少一个合并的虚拟多线，其中所述至少一个合并虚拟多线具有符合类型-1单元的默认多音调的第一部分和符合非默认的第二部分 2型细胞的聚间距。

32. 发明申请

US20100127333A1 NOVEL LAYOUT ARCHITECTURE FOR PERFORMANCE ENHANCEMENT 审中-公开
标题翻译：性能增强的新型布局架构
公开(公告)号：US20100127333A1
公开(公告)日：2010-05-27
申请号：US12276172
申请日：2008-11-21
申请人： Yung-Chin Hou , Ta-Pen Guo , Harry Chuang , Carlos H. Diaz , Lee-Chung Lu , Li-Chun Tien , Oscar M. K. Law , Chih-Chiang Chang , Chun-Hui Tai , Jonathan Lee
发明人： Yung-Chin Hou , Ta-Pen Guo , Harry Chuang , Carlos H. Diaz , Lee-Chung Lu , Li-Chun Tien , Oscar M. K. Law , Chih-Chiang Chang , Chun-Hui Tai , Jonathan Lee
IPC分类号： H01L27/092 , H01L27/088
CPC分类号： H01L27/0207 , H01L21/823418 , H01L21/823481
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes an active region in a semiconductor substrate; a first field effect transistor (FET) disposed in the active region; and an isolation structure disposed in the active region. The FET includes a first gate; a first source formed in the active region and disposed on a first region adjacent the first gate from a first side; and a first drain formed in the active region and disposed on a second region adjacent the first gate from a second side. The isolation structure includes an isolation gate disposed adjacent the first drain; and an isolation source formed in the active region and disposed adjacent the isolation gate such that the isolation source and the first drain are on different sides of the isolation gate.
摘要翻译：本发明提供集成电路。集成电路包括半导体衬底中的有源区; 设置在有源区中的第一场效应晶体管（FET）以及设置在有源区域中的隔离结构。 FET包括第一栅极; 形成在所述有源区中并且从第一侧设置在与所述第一栅极相邻的第一区域上的第一源极; 以及形成在所述有源区中并且从第二侧设置在与所述第一栅极相邻的第二区域上的第一漏极。隔离结构包括邻近第一漏极设置的隔离栅极; 以及隔离源，形成在所述有源区中并邻近所述隔离栅设置，使得所述隔离源和所述第一漏极位于所述隔离栅极的不同侧上。

33. 发明申请

US20070109832A1 ECO cell for reducing leakage power 有权
标题翻译： ECO电池用于减少泄漏电力
公开(公告)号：US20070109832A1
公开(公告)日：2007-05-17
申请号：US11281035
申请日：2005-11-17
申请人： Yung-Chin Hou , Lee-Chung Lu , Chu-Ping Wang , Li-Chun Tien
发明人： Yung-Chin Hou , Lee-Chung Lu , Chu-Ping Wang , Li-Chun Tien
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H01L27/0207
摘要： A semiconductor structure includes a first conductive line for connecting to a power supply, and a second conductive line for connecting to a complementary power supply. At least one spare cell is decoupled from the first or second conductive line for being selectively connected to at lease one normal cell, the first conductive line and the second conductive line only when an engineering change order is placed.
摘要翻译：半导体结构包括用于连接到电源的第一导线和用于连接到互补电源的第二导线。至少一个备用单元与第一或第二导线分离，以便仅当放置工程改变顺序时才有选择地连接到至少一个正常单元，第一导线和第二导线。

34. 发明授权

US09608604B2 Voltage level shifter with single well voltage 有权
公开(公告)号：US09608604B2
公开(公告)日：2017-03-28
申请号：US11639006
申请日：2006-12-14
申请人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
发明人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
IPC分类号： H03L5/00 , H03K3/356
CPC分类号： H03K3/35613
摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

35. 发明授权

US08607172B2 Integrated circuits and methods of designing the same 有权
标题翻译：集成电路及其设计方法
公开(公告)号：US08607172B2
公开(公告)日：2013-12-10
申请号：US13267310
申请日：2011-10-06
申请人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang , Mei-Hui Huang
发明人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang , Mei-Hui Huang
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068 , G06F17/5077 , H01L27/11807 , H01L2027/11875 , H01L2027/11885
摘要： A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.
摘要翻译：设计集成电路的方法包括在第一标准单元中部署有效区域。至少一个栅电极被路由，与第一标准单元中的有效区重叠。至少一个金属线结构被路由，与第一标准单元中的有效区重叠。至少一个金属线结构基本上平行于栅电极。第一电源轨道基本上正交于第一标准单元中的至少一个金属线结构。第一电力轨与至少一个金属线结构重叠。第一动力轨具有与至少一个金属线结构相邻的平坦边缘。第一连接插头部署在第一电力轨道与第一标准单元中的至少一个金属线结构重叠的区域处。

36. 发明授权

US08504972B2 Standard cells having flexible layout architecture/boundaries 有权
标题翻译：具有灵活布局架构/边界的标准单元
公开(公告)号：US08504972B2
公开(公告)日：2013-08-06
申请号：US12697887
申请日：2010-02-01
申请人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
发明人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.
摘要翻译：集成电路布局包括标准单元，其包括彼此平行并具有栅极间距的第一栅极条和第二栅极条; 在第一标准单元的相对端上的第一边界和第二边界; 以及在第一标准单元的相对端上并且平行于第一栅极条和第二栅极条的第三边界和第四边界。第三边界和第四边界之间的单元间距不等于门间距的整数倍。 PMOS晶体管由第一栅极条和第一有源区形成。 NMOS晶体管由第一栅极条和第二有源区形成。

37. 发明申请

US20120131528A1 METHOD AND APPARATUS FOR ACHIEVING MULTIPLE PATTERNING TECHNOLOGY COMPLIANT DESIGN LAYOUT 有权
标题翻译：实现多种图案技术的方法和装置合规设计布局
公开(公告)号：US20120131528A1
公开(公告)日：2012-05-24
申请号：US12953661
申请日：2010-11-24
申请人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
发明人： Huang-Yu Chen , Fang-Yu Fan , Yuan-Te Hou , Lee-Chung Lu , Ru-Gun Liu , Ken-Hsien Hsieh , Lee Fung Song , Wen-Chun Huang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G03F7/70433 , G03F7/70466
摘要： A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved. If the pattern layout is a multiple patterning compliant layout, the method includes coloring each of the plurality of features based on the color of each feature's corresponding at least one routing track, thereby forming a colored pattern layout, and generating at least two masks with the features of the colored pattern layout. Each mask includes features of a single color.
摘要翻译：提供了一种用于实现多个图案化兼容技术设计布局的方法和装置。示例性方法包括提供具有路由轨迹的路由网格; 指定每个路线轨道至少两种颜色之一; 将具有多个特征的图案布局应用于所述路由网格，其中所述多个特征中的每一个对应于至少一个路由轨道; 以及应用特征分解约束来确定所述图案布局是否是符合多重图案化的布局。如果图案布局不是符合多重图案化的布局，则可以修改图案布局，直到实现多重图案化兼容布局。如果图案布局是符合多重图案化的布局，则该方法包括基于每个特征对应的至少一个路线轨迹的颜色来着色多个特征中的每一个，从而形成彩色图案布局，并且生成至少两个具有彩色图案布局的特点。每个面具都包含单一颜色的特征。

38. 发明申请

US20100269081A1 Standard Cells Having Flexible Layout Architecture/Boundaries 有权
标题翻译：具有灵活布局架构/边界的标准单元
公开(公告)号：US20100269081A1
公开(公告)日：2010-10-21
申请号：US12697887
申请日：2010-02-01
申请人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
发明人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.
摘要翻译：集成电路布局包括标准单元，其包括彼此平行并具有栅极间距的第一栅极条和第二栅极条; 在第一标准单元的相对端上的第一边界和第二边界; 以及在第一标准单元的相对端上并且平行于第一栅极条和第二栅极条的第三边界和第四边界。第三边界和第四边界之间的单元间距不等于门间距的整数倍。 PMOS晶体管由第一栅极条和第一有源区形成。 NMOS晶体管由第一栅极条和第二有源区形成。

39. 发明授权

US07458051B2 ECO cell for reducing leakage power 有权
标题翻译： ECO电池用于减少泄漏电力
公开(公告)号：US07458051B2
公开(公告)日：2008-11-25
申请号：US11281035
申请日：2005-11-17
申请人： Yung-Chin Hou , Lee-Chung Lu , Chu-Ping Wang , Li-Chun Tien
发明人： Yung-Chin Hou , Lee-Chung Lu , Chu-Ping Wang , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G11C5/063 , H01L27/0207
摘要： A semiconductor structure including at least one spare cell is disclosed. The semiconductor structure includes a first conductive line coupled to a power supply, and a second conductive line coupled to a complementary power supply. At least one spare cell is decoupled from the first or second conductive line for being selectively connected to at least one normally functioning electronic components, the first conductive line and the second conductive line only during a rerouting process for reducing leakage power of the semiconductor structure.
摘要翻译：公开了包括至少一个备用单元的半导体结构。半导体结构包括耦合到电源的第一导线和耦合到互补电源的第二导线。至少一个备用单元与第一或第二导线分离，以便仅在用于减小半导体结构的泄漏功率的重新路由过程中选择性地连接到至少一个正常工作的电子部件，第一导线和第二导线。

40. 发明授权

US09337290B2 Layout architecture for performance improvement 有权
标题翻译：布局架构，提升性能
公开(公告)号：US09337290B2
公开(公告)日：2016-05-10
申请号：US13537804
申请日：2012-06-29
申请人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
发明人： Lee-Chung Lu , Li-Chun Tien , Hui-Zhong Zhuang
IPC分类号： H01L29/423 , H01L29/417 , H01L27/32 , H01L27/02 , H01L21/768
CPC分类号： H01L21/823475 , H01L21/32055 , H01L21/76802 , H01L21/76895 , H01L21/823418 , H01L27/0207 , H01L27/326 , H01L29/0649 , H01L29/41725 , H01L29/41775 , H01L29/4238
摘要： An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.
摘要翻译：提供集成电路。集成电路包括设置在第一源极/漏极区域上的第一触点，设置在第二源极/漏极区域上的第二触点，设置在栅极上的多晶硅，插入在第一触点和第二触点之间的多晶硅，第一多晶硅在有源区内桥接多晶硅和第一接触，以及电耦合到第一多晶硅接触的输出结构。

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