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1. 发明申请

US20080143418A1 Voltage level shifter with single well voltage 有权
标题翻译：具有单井电压的电压电平转换器
公开(公告)号：US20080143418A1
公开(公告)日：2008-06-19
申请号：US11639006
申请日：2006-12-14
申请人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
发明人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
IPC分类号： H03L5/00
CPC分类号： H03K3/35613
摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.
摘要翻译：本发明公开了一种电压电平转换器，它包括具有栅极，源极和体耦合到输入端的第一P型金属氧化物半导体（PMOS）晶体管，第一正电压电源和第二正电压电源，以及分别具有源极，漏极和体耦合到第三正电压电源，输出节点和第二正电压电源的第二PMOS晶体管，其中形成第一和第二PMOS晶体管在一个Nwell。

2. 发明授权

US09608604B2 Voltage level shifter with single well voltage 有权
公开(公告)号：US09608604B2
公开(公告)日：2017-03-28
申请号：US11639006
申请日：2006-12-14
申请人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
发明人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
IPC分类号： H03L5/00 , H03K3/356
CPC分类号： H03K3/35613
摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

3. 发明授权

US07966596B2 Place-and-route layout method with same footprint cells 有权
标题翻译：具有相同占位面积单元格的布局和布局方法
公开(公告)号：US07966596B2
公开(公告)日：2011-06-21
申请号：US12199617
申请日：2008-08-27
申请人： Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
发明人： Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
IPC分类号： G06F17/50 , G06F11/22
CPC分类号： G06F17/5077
摘要： This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.
摘要翻译：本发明公开了一种自动生成集成电路（IC）布局的方法，该方法包括：确定第一单元高度，创建全部具有第一单元高度的多个标准单元，以及通过以下步骤从多个标准单元生成IC布局放置和布线。

4. 发明申请

US20100058267A1 PLACE-AND-ROUTE LAYOUT METHOD WITH SAME FOOTPRINT CELLS 有权
标题翻译：具有相同FOOTPRINT细胞的布置和路由布局方法
公开(公告)号：US20100058267A1
公开(公告)日：2010-03-04
申请号：US12199617
申请日：2008-08-27
申请人： Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
发明人： Lee-Chung Lu , Chung-Hsing Wang , Ping Chung Li , Chun-Hui Tai , Li-Chun Tien , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： This invention discloses a method for automatically generating an integrated circuit (IC) layout, the method comprises determining a first cell height, creating a plurality of standard cells all having the first cell height, and generating the IC layout from the plurality of standard cells by placing and routing thereof.
摘要翻译：本发明公开了一种自动生成集成电路（IC）布局的方法，该方法包括：确定第一单元高度，创建全部具有第一单元高度的多个标准单元，以及通过以下步骤从多个标准单元生成IC布局放置和布线。

5. 发明申请

US20080270813A1 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US20080270813A1
公开(公告)日：2008-10-30
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路以及耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

6. 发明授权

US07793130B2 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US07793130B2
公开(公告)日：2010-09-07
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路和耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

7. 发明授权

US07640520B2 Design flow for shrinking circuits having non-shrinkable IP layout 有权
标题翻译：具有不可收缩IP布局的收缩电路的设计流程
公开(公告)号：US07640520B2
公开(公告)日：2009-12-29
申请号：US11807640
申请日：2007-05-30
申请人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
摘要翻译：提供了一种用于处理集成电路的方法。该方法包括提供具有第一标度的第一集成电路，其中第一集成电路包括包含第一知识产权（IP）布局的可收缩电路和包括第二IP布局的不可收缩电路; 以及生成具有小于所述第一刻度的第二刻度的第二集成电路。产生第二集成电路的步骤包括将可收缩集成电路收缩到第二刻度。该方法还包括将第二IP布局与不可收缩电路合并以产生最终集成电路。

8. 发明授权

US08671367B2 Integrated circuit design in optical shrink technology node 有权
标题翻译：光收缩技术节点集成电路设计
公开(公告)号：US08671367B2
公开(公告)日：2014-03-11
申请号：US12340294
申请日：2008-12-19
申请人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Yung-Chin Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/505
摘要： Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.
摘要翻译：公开了一种用于设计使用光收缩技术节点提供的电路和/或IC芯片的系统，方法和计算机可读介质。可以在第一技术节点中提供初始设计数据，并且通过在设计流程的一个或多个EDA工具中使用嵌入缩放因子，可以为光收缩技术节点中的电路生成设计（例如，掩模数据）。可以提供嵌入式缩放因子的EDA工具的示例是包括LPE卡片和RC提取技术文件的模拟模型和提取工具。

9. 发明申请

US20080229259A1 Design flow for shrinking circuits having non-shrinkable IP layout 有权
标题翻译：具有不可收缩IP布局的收缩电路的设计流程
公开(公告)号：US20080229259A1
公开(公告)日：2008-09-18
申请号：US11807640
申请日：2007-05-30
申请人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
摘要翻译：提供了一种用于处理集成电路的方法。该方法包括提供具有第一刻度的第一集成电路，其中第一集成电路包括包含第一知识产权（IP）布局的可收缩电路和包括第二IP布局的不可收缩电路; 以及生成具有小于所述第一刻度的第二刻度的第二集成电路。产生第二集成电路的步骤包括将可收缩集成电路收缩到第二刻度。该方法还包括将第二IP布局与不可收缩电路合并以产生最终集成电路。

10. 发明授权

US06862723B1 Methodology of generating antenna effect models for library/IP in VLSI physical design 失效
标题翻译：在VLSI物理设计中为库/ IP生成天线效应模型的方法
公开(公告)号：US06862723B1
公开(公告)日：2005-03-01
申请号：US10263542
申请日：2002-10-03
申请人： Chung-Hsing Wang , Daisy Wang , Chia Ling Cheng , Lee Chung Lu , Cliff Hou
发明人： Chung-Hsing Wang , Daisy Wang , Chia Ling Cheng , Lee Chung Lu , Cliff Hou
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： A new method to route a metal line in the layout of an integrated circuit device is achieved. The method comprises providing a layout for an integrated circuit device comprising an array of placed standard cells. Contact/via layer polygons are placed for coupling the standard cells. A line is routed in a metal layer. An antenna effect value is calculated for the line using parameters previously determined from the layout of each the standard cell. The parameters comprise gate area, diode area, metal area, and contact/via area coupled to the line. The gate area, the diode area, the metal area, and the contact/via area are segregated by metal level. The steps of routing and calculating are repeated if the antenna effect value exceeds a specified value. A method to extract parameters is disclosed.
摘要翻译：实现了在集成电路器件的布局中布线金属线路的新方法。该方法包括提供包括放置的标准单元阵列的集成电路器件的布局。放置接触/通过层多边形来连接标准细胞。线路在金属层中。使用从每个标准单元的布局预先确定的参数来计算行的天线效应值。参数包括栅极面积，二极管面积，金属面积，以及耦合到线路的接触/通孔面积。栅极区域，二极管区域，金属区域和接触/通孔区域被金属层隔离。如果天线效应值超过指定值，则重复路由和计算步骤。公开了提取参数的方法。

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