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31. 发明授权

US07721171B2 Scheme to optimize scan chain ordering in designs 有权
标题翻译：优化设计中扫描链排序的方案
公开(公告)号：US07721171B2
公开(公告)日：2010-05-18
申请号：US11839648
申请日：2007-08-16
申请人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
发明人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
IPC分类号： G01R31/28
CPC分类号： G01R31/318591 , G06F17/505 , G06F2217/14
摘要： A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.
摘要翻译：提供了一种在电子计算机辅助设计系统中优化电路设计中的扫描链排序的方法。该方法包括：创建具有第一单元和第二单元的电路设计的示意图，第一单元和第二单元各自在其中具有锁存器; 为第一个单元中的每个锁存器和原理图上的第二个单元创建扫描输入引脚和扫描输出引脚; 在原理图上产生第一标签以提供用于电路设计中的锁存器的第一布线布置，第一布线布置识别每个锁存器的扫描输入被连接到另一个的另一个的扫描输出的第一顺序锁存器创建一个代表电路设计的布局; 基于第一布线布置在布局上产生具有第一长度的第一扫描链; 在所述布局上从所述第一扫描链创建第二扫描链，所述第二扫描链具有小于所述第一扫描链的所述第一长度的第二长度; 并且基于所述第二扫描链在所述原理图上产生第二标签，所述第二标签为所述电路设计中的所述锁存器提供第二布线布置，所述第二布线布置识别每个所述闩锁的扫描输入的第二顺序连接到另一个锁存器的扫描输出。

32. 发明申请

US20090177870A1 Method and System for a Wiring-Efficient Permute Unit 失效
标题翻译：一种有效的宽带单元的方法和系统
公开(公告)号：US20090177870A1
公开(公告)日：2009-07-09
申请号：US11968692
申请日：2008-01-03
申请人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
发明人： Bruce M. Fleischer , Hung C. Ngo , Jun Sawada
IPC分类号： G06F9/305 , G06F13/00
CPC分类号： G06F9/30032 , G06F7/762 , G06F7/766 , G06F9/30036 , G06F9/3824 , G06F9/3826
摘要： A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple multiplexors (MUXs) coupled to multiple logical AND gates. The multiple logical AND gates are coupled to multiple logical OR gates. The logical AND gates are physically separated from the logical OR gates. The logical AND gates receive input from one or more output data signals from the selectors. The logical OR gates combine the one or more output signals from the logical AND gates and provide output data from the permute unit.
摘要翻译：一种在置换单元中提供布线效率的方法。多个选择器从多个寄存器文件接收输入数据和共享控制信号。置换单元包括耦合到多个逻辑与门的多个多路复用器（MUX）。多个逻辑与门被耦合到多个逻辑或门。逻辑“与”门与逻辑或门物理分离。逻辑与门接收来自选择器的一个或多个输出数据信号的输入。逻辑或门组合来自逻辑与门的一个或多个输出信号，并提供来自置换单元的输出数据。

33. 发明授权

US5471188A Fast comparator circuit 失效
标题翻译：快速比较电路
公开(公告)号：US5471188A
公开(公告)日：1995-11-28
申请号：US320477
申请日：1994-10-07
申请人： Barbara A. Chappell , Terry I. Chappell , Bruce M. Fleischer , Stanley E. Schuster
发明人： Barbara A. Chappell , Terry I. Chappell , Bruce M. Fleischer , Stanley E. Schuster
IPC分类号： G06F7/04 , G06F7/02
CPC分类号： G06F7/02
摘要： A fast comparator circuit, including a plurality of first switches operating in parallel. A first data bit from a first data word is input into a first input of each first switch, and a corresponding second data bit from a second data word is respectively input into a second input of each first switch. Each first switch provides a first logic state output when the first data bit matches the corresponding second data bit or a second logic state output when the first data bit does not match the second data bit. A plurality of second switches receive the respective logic state outputs and produce a combined output, indicating an all match or a mismatch, to a third switch combination connected to a first branch node and a second branch node to create a first voltage difference between the first and second branch nodes when an all match output results and a second voltage difference between the first and second branch node when a mismatch output results. A sense amplifier operates to amplify the voltage differentials that develope due to an imbalance caused in the conductance at the two branch nodes.
摘要翻译：一种快速比较器电路，包括并行操作的多个第一开关。来自第一数据字的第一数据位被输入到每个第一开关的第一输入端，并且来自第二数据字的对应的第二数据位分别输入到每个第一开关的第二输入端。当第一数据位与第二数据位匹配时，每个第一开关提供第一逻辑状态输出，或者当第一数据位与第二数据位不匹配时提供第二逻辑状态输出。多个第二开关接收相应的逻辑状态输出并产生指示全部匹配或不匹配的组合输出到连接到第一分支节点和第二分支节点的第三开关组合，以在第一和第二分支节点之间产生第一电压差以及当匹配输出结果时，第二分支节点和第一和第二分支节点之间的第二电压差得到结果。感测放大器用于放大由于在两个分支节点处的电导引起的不平衡而发展的电压差。

34. 发明授权

US09652231B2 All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture 有权
公开(公告)号：US09652231B2
公开(公告)日：2017-05-16
申请号：US12250584
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F9/315 , G06F7/76 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F7/76 , G06F9/30025 , G06F9/30032 , G06F9/3887
摘要： Mechanisms are provided for dynamic data driven alignment and data formatting in a floating point SIMD architecture. At least two operand inputs are input to a permute unit of a processor. Each operand input contains at least one floating point value upon which a permute operation is to be performed by the permute unit. A control vector input, having a plurality of floating point values that together constitute the control vector input, is input to the permute unit of the processor for controlling the permute operation of the permute unit. The permute unit performs a permute operation on the at least two operand inputs according to a permutation pattern specified by the plurality of floating point values that constitute the control vector input. Moreover, a result output of the permute operation is output from the permute unit to a result vector register of the processor.

35. 发明授权

US07865693B2 Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type 失效
标题翻译：使用指示相对于精度类型的元素边界的偏移的掩码对齐精确转换的矢量数据
公开(公告)号：US07865693B2
公开(公告)日：2011-01-04
申请号：US12250599
申请日：2008-10-14
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer , Michael K. Gschwind
IPC分类号： G06F15/16
CPC分类号： G06F9/30032 , G06F9/30025 , G06F9/30036 , G06F9/3887
摘要： Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurality of vector elements. The first precision type is modified to have a second precision type different in precision than the first precision type to thereby generate at least one modified data value. The at least one modified data value is stored in at least one vector element of the plurality of vector elements. An alignment of the at least one modified data value is determined relative to a boundary of a vector element of the vector register. An alignment operation to re-align the at least one modified data value based on the boundary of the vector element of the vector register is performed.
摘要翻译：提供了基于减少的精度数据值对准增强精度向量的机制。接收具有第一精度类型的至少一个数据值以存储在向量寄存器中。向量寄存器将数据存储为具有多个向量元素的向量。第一精度类型被修改为具有与第一精度类型不同的第二精度类型，从而生成至少一个修改的数据值。所述至少一个修改的数据值存储在所述多个向量元素的至少一个向量元素中。相对于向量寄存器的向量元素的边界确定至少一个经修改的数据值的对齐。执行基于向量寄存器的向量元素的边界来重新对准至少一个修改的数据值的对准操作。

36. 发明申请

US20100218155A1 Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design 失效
标题翻译：物理综合分层设计中的自动关键区域分配
公开(公告)号：US20100218155A1
公开(公告)日：2010-08-26
申请号：US12394035
申请日：2009-02-26
申请人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Hoaxing Ren
发明人： Bruce M. Fleischer , David J. Geiger , Hung C. Ngo , Ruchir Puri , Hoaxing Ren
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/84
摘要： A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other.Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.
摘要翻译：公开了一种用于在分级集成电路设计中有效执行时序关键单元级单元的自动布置的方法，计算机程序产品和数据处理系统。为了准备全局优化，在单元级别的整个单元，宏级单元被分配一个“放置力”，其用于限制宏级单元从其当前位置的移动。还定义每个宏元素的移动边界，以便将给定宏元素中的组件保持在彼此相对接近。然后，通过力导向布局算法，在设计的“扁平化”模型上执行单元设计的优化/放置，同时遵循移动边界。在这种“扁平化”优化之后，放置的“单位级”单元被建模为阻塞，并且宏元素被单独地优化，同时尊重阻塞的位置。重复这个整个过程，直到单元布局的优化最终收敛。

37. 发明授权

US07739323B2 Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator 失效
标题翻译：用于提供组合模9和3残留发生器的系统，方法和计算机程序产品
公开(公告)号：US07739323B2
公开(公告)日：2010-06-15
申请号：US11425185
申请日：2006-06-20
申请人： Daniel Lipetz , Bruce M. Fleischer , Eric M. Schwarz
发明人： Daniel Lipetz , Bruce M. Fleischer , Eric M. Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/72 , G06F7/727
摘要： Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator. The methods include receiving a number in binary coded decimal (BCD) or binary format. A modulus-9 residue of the number is calculated. The modulus-9 residue that is calculated includes a modulus-3 residue of the number. The modulus-3 residue of the number is output. If the number is in BCD format, then the modulus-9 residue of the number is output.
摘要翻译：用于提供组合模9和3残留发生器的系统，方法和计算机程序产品。这些方法包括接收二进制编码十进制（BCD）或二进制格式的数字。计算该数的模数-9残基。计算的模数-9残基包括该数目的模数-3残基。输出该数的模数-3残差。如果数字为BCD格式，则输出数字的模数-9个残差。

38. 发明授权

US07730117B2 System and method for a floating point unit with feedback prior to normalization and rounding 失效
标题翻译：在归一化和舍入之前具有反馈的浮点单元的系统和方法
公开(公告)号：US07730117B2
公开(公告)日：2010-06-01
申请号：US11054110
申请日：2005-02-09
申请人： Bruce M. Fleischer , Juergen Haess , Michael Kroener , Martin S. Schmookler , Eric M. Schwarz , Son Dao-Trong
发明人： Bruce M. Fleischer , Juergen Haess , Michael Kroener , Martin S. Schmookler , Eric M. Schwarz , Son Dao-Trong
IPC分类号： G06F7/38 , G06F15/00
CPC分类号： G06F7/483 , G06F7/499 , G06F7/49936 , G06F7/49947 , G06F7/5443 , G06F2207/382
摘要： A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
摘要翻译：一种用于执行浮点算术运算的系统，包括适于接收操作数的输入寄存器。该系统还包括响应于确定操作数处于非归一化格式而执行移位或掩蔽操作的机制。该系统还包括用于响应于确定操作数是单一精度来执行操作数的单精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作未执行递增。操作数是在以前的操作中创建的。该系统还包括响应于确定操作数是双精度来执行操作数的双精度递增的指令，操作数需要基于先前操作的结果而增加，并且先前的操作不执行递增。

39. 发明申请

US20090049353A1 SCHEME TO OPTIMIZE SCAN CHAIN ORDERING IN DESIGNS 有权
标题翻译：计划优化设计中的链条订单
公开(公告)号：US20090049353A1
公开(公告)日：2009-02-19
申请号：US11839648
申请日：2007-08-16
申请人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
发明人： Mark A. Erle , Bruce M. Fleischer , Daniel Lipetz
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318591 , G06F17/505 , G06F2217/14
摘要： A method for optimizing a scan chain ordering in circuit designs in an electronic computer-aided design system is provided. The method comprising: creating a schematic representative of a circuit design having a first cell and a second cell, the first cell and the second cell each having latches therein; creating a scan input pin and a scan output pin for each of the latches in the first cell and the second cell on the schematic; generating a first label on the schematic to provide a first wiring arrangement for the latches in the circuit design, the first wiring arrangement identifies a first order to which the scan input of each of the latches is wired to the scan output of another one of the latches; creating a layout representative of the circuit design; generating a first scan chain having a first length on the layout based on the first wiring arrangement; creating a second scan chain from the first scan chain on the layout, the second scan chain having a second length less than the first length of the first scan chain; and generating a second label on the schematic based on the second scan chain, the second label provides a second wiring arrangement for the latches in the circuit design, the second wiring arrangement identifies a second order to which the scan input of each of the latches is wired to the scan output of another one of the latches.
摘要翻译：提供了一种在电子计算机辅助设计系统中优化电路设计中的扫描链排序的方法。该方法包括：创建具有第一单元和第二单元的电路设计的示意图，第一单元和第二单元各自在其中具有锁存器; 为第一个单元中的每个锁存器和原理图上的第二个单元创建扫描输入引脚和扫描输出引脚; 在原理图上产生第一标签以提供用于电路设计中的锁存器的第一布线布置，第一布线布置识别每个锁存器的扫描输入被连接到另一个的另一个的扫描输出的第一顺序锁存器创建一个代表电路设计的布局; 基于第一布线布置在布局上产生具有第一长度的第一扫描链; 在所述布局上从所述第一扫描链创建第二扫描链，所述第二扫描链具有小于所述第一扫描链的所述第一长度的第二长度; 并且基于所述第二扫描链在所述原理图上产生第二标签，所述第二标签为所述电路设计中的所述锁存器提供第二布线布置，所述第二布线布置识别每个所述闩锁的扫描输入的第二顺序连线到另一个锁存器的扫描输出。

40. 发明授权

US09575753B2 SIMD compare instruction using permute logic for distributed register files 有权
标题翻译： SIMD比较指令使用分布式寄存器文件的置换逻辑
公开(公告)号：US09575753B2
公开(公告)日：2017-02-21
申请号：US13420699
申请日：2012-03-15
申请人： Alexandre E. Eichenberger , Bruce M. Fleischer
发明人： Alexandre E. Eichenberger , Bruce M. Fleischer
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30032 , G06F9/30021 , G06F9/30036 , G06F9/3838
摘要： Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations.
摘要翻译：提供了一种包括用于对至少两个输入向量寄存器的向量元素值进行数据相关性检查操作的单指令多数据（SIMD）处理器的数据处理系统中的机制。执行对SIMD检查指令的两次调用，其中一个具有输入向量寄存器具有第一级，一个具有不同顺序的输入向量寄存器。 simd检查指令执行比较以确定是否存在任何数据依赖性。获得对simd检查指令的两次调用的结果，并用于确定至少两个输入向量寄存器中是否存在任何数据依赖性。基于该结果，SIMD处理器可以执行各种操作。

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