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31. 发明申请

US20060134906A1 Post-ESL porogen burn-out for copper ELK integration 有权
标题翻译：用于铜ELK整合的后ESL致孔剂烧尽
公开(公告)号：US20060134906A1
公开(公告)日：2006-06-22
申请号：US11020372
申请日：2004-12-22
申请人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
发明人： Yung-Cheng Lu , Ying-Tsung Chen , Zhen-Cheng Wu , Pi-Tsung Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/3148 , H01L21/31695 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L2221/1047
摘要： A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.
摘要翻译：提供一种制造具有多孔低k电介质层的半导体器件的方法。优选的实施方案包括在镶嵌工艺中形成含致孔剂的低k电介质层的步骤。在优选的实施方案中，通过电子束致孔剂降解的孔产生在CMP平坦化镶嵌铜导体并沉积半透膜盖层的步骤之后发生。在替代实施例中，盖层基本上由碳化硅，氮化硅，Co，W，Al，Ta，Ti，Ni，Ru及其组合组成。半透膜盖层优选在PECVD条件下沉积，使得盖层具有足够的可渗透性以能够除去致孔剂降解副产物。优选实施方案还包括在沉积半透膜盖层之前的原位N 2 / NH 3 N 3处理。

32. 发明授权

US07056826B2 Method of forming copper interconnects 失效
标题翻译：形成铜互连的方法
公开(公告)号：US07056826B2
公开(公告)日：2006-06-06
申请号：US10337684
申请日：2003-01-07
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Ying-Tsung Chen , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Ying-Tsung Chen , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming copper interconnects for an integrated circuit is provided. An antireflective coating layer is formed over an insulating layer formed over a semiconductor substrate. An interconnect pattern is patterned and etched into said insulating layer. A diffusion barrier layer is then conformally deposited in a deposition chamber along the etched interconnect pattern, wherein the antireflective coating is removed in said chamber before deposition of the barrier layer. Copper interconnects are then formed in the interconnect pattern etched in the insulating layer.
摘要翻译：提供一种形成用于集成电路的铜互连的方法。在半导体衬底上形成的绝缘层上形成抗反射涂层。将互连图案图案化并蚀刻到所述绝缘层中。然后沿着蚀刻的互连图案将扩散阻挡层共形沉积在沉积室中，其中在沉积阻挡层之前在所述室中去除抗反射涂层。然后在绝缘层中蚀刻的互连图案中形成铜互连。

33. 发明申请

US20050236694A1 Silicon oxycarbide and silicon carbonitride based materials for MOS devices 有权
标题翻译：用于MOS器件的碳氧化硅和碳氮化硅基材料
公开(公告)号：US20050236694A1
公开(公告)日：2005-10-27
申请号：US10895514
申请日：2004-07-21
申请人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
发明人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
IPC分类号： H01L21/31 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/768 , H01L23/31 , H01L23/58 , H01L29/49
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/3192 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.
摘要翻译：在优选实施例中，在基板上形成栅极电介质和电极。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。间隔物优选由SiCO基材料或SiCN基材料形成。然后形成源极和漏极。在源极/漏极区域和间隔物上形成接触蚀刻停止层（CES）层。 CES层优选由SiCO基材料或SiCN基材料形成。然后在CES层上形成级间介质（ILD）。

34. 发明授权

US06878621B2 Method of fabricating barrierless and embedded copper damascene interconnects 失效
标题翻译：制造无障碍和嵌入铜大马士革互连的方法
公开(公告)号：US06878621B2
公开(公告)日：2005-04-12
申请号：US10346382
申请日：2003-01-17
申请人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76835 , H01L21/76885
摘要： A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.
摘要翻译：一种形成至少一个无障碍嵌入金属结构的方法，包括以下步骤。具有形成在其上的图案化电介质层的结构，其中至少一个开口暴露出结构的至少一个相应部分。在每个相应的开口内形成相应的金属结构。去除第一电介质层以暴露相应的至少一个金属结构的顶部和至少一部分侧壁。介电阻挡层形成在相应的金属结构的结构和暴露的顶部上。在电介质阻挡层上方形成第二个保形介电层，以完成嵌入在第二保形电介质层内的相应无障碍的至少一个金属结构。电介质阻挡层防止包含相应的至少一种金属结构的金属扩散到第二保形电介质层中。

35. 发明授权

US09136226B2 Impurity doped UV protection layer 有权
标题翻译：杂质掺杂紫外线保护层
公开(公告)号：US09136226B2
公开(公告)日：2015-09-15
申请号：US12774569
申请日：2010-05-05
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Chung-Chi Ko
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Chung-Chi Ko
IPC分类号： H01L21/31 , H01L23/552
CPC分类号： H01L23/552 , B01D53/9468 , B01D53/9472 , B01D2255/1021 , B01D2255/9022 , B01D2255/9035 , B01D2255/9155 , B01D2257/404 , B01D2257/502 , B01D2257/702 , B01J23/40 , B01J23/42 , B01J29/061 , B01J29/072 , B01J29/763 , B01J35/0006 , B01J35/04 , B01J37/024 , B01J37/0244 , B01J37/0246 , H01L2924/0002 , H01L2924/00
摘要： An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.
摘要翻译：在沉积紫外线固化介电层之前，在半导体工件上形成紫外（UV）保护层。紫外线防护层防止紫外线到达并损坏下层材料层和电气设备。 UV保护层包括掺杂有杂质的硅层，其中杂质包括O，C，H，N或其组合。作为实例，UV保护层可以包括SiOC：H，SiON，SiN，SiCO：H，它们的组合或多层。

36. 发明授权

US08952244B2 Solar cell 有权
标题翻译：太阳能电池
公开(公告)号：US08952244B2
公开(公告)日：2015-02-10
申请号：US13089321
申请日：2011-04-19
申请人： Yen-Cheng Hu , Peng Chen , Shuo-Wei Liang , Zhen-Cheng Wu
发明人： Yen-Cheng Hu , Peng Chen , Shuo-Wei Liang , Zhen-Cheng Wu
IPC分类号： H01L31/00 , H01L31/0216 , H01L31/0224 , H01L31/0352 , H01L31/068
CPC分类号： H01L31/02168 , H01L31/022441 , H01L31/035209 , H01L31/035227 , H01L31/0682 , Y02E10/547
摘要： A solar cell includes a semiconductor substrate, a doping layer, a quantum well layer, a first passivation layer, a second passivation layer, a first electrode and a second electrode. The semiconductor substrate has a front surface and a back surface, and the front surface of the semiconductor substrate includes nano-rods. The doping layer covers the surface of the nano-rods. The electrode layers cover the doping layer. The quantum well layer having at least one first doping region and at least one second doping region is disposed on the semiconductor substrate. The quantum well layer includes polycrystalline silicon germanium (Si1-xGex). The first passivation layer and the second passivation layer cover the first and the second doping regions of the quantum well layer, respectively. The first electrode and the second electrode are electrically connected to the first doping region and the second doping region of the quantum well layer, respectively.
摘要翻译：太阳能电池包括半导体衬底，掺杂层，量子阱层，第一钝化层，第二钝化层，第一电极和第二电极。半导体衬底具有前表面和后表面，并且半导体衬底的前表面包括纳米棒。掺杂层覆盖纳米棒的表面。电极层覆盖掺杂层。具有至少一个第一掺杂区域和至少一个第二掺杂区域的量子阱层设置在半导体衬底上。量子阱层包括多晶硅锗（Si1-xGex）。第一钝化层和第二钝化层分别覆盖量子阱层的第一和第二掺杂区域。第一电极和第二电极分别电连接到量子阱层的第一掺杂区域和第二掺杂区域。

37. 发明授权

US08456009B2 Semiconductor structure having an air-gap region and a method of manufacturing the same 有权
标题翻译：具有气隙区域的半导体结构及其制造方法
公开(公告)号：US08456009B2
公开(公告)日：2013-06-04
申请号：US12707969
申请日：2010-02-18
申请人： Shu-Hui Su , Cheng-Lin Huang , Jiing-Feng Yang , Zhen-Cheng Wu , Ren-Guei Wu , Dian-Hau Chen , Yuh-Jier Mii
发明人： Shu-Hui Su , Cheng-Lin Huang , Jiing-Feng Yang , Zhen-Cheng Wu , Ren-Guei Wu , Dian-Hau Chen , Yuh-Jier Mii
IPC分类号： H01L29/40
CPC分类号： H01L23/5226 , H01L21/02203 , H01L21/76805 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76834 , H01L21/76897 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.
摘要翻译：半导体结构包括第一含金属层，电介质覆盖层，第二含金属层和导电焊盘。第一含金属层包括一组金属结构，设置成占据第一含金属层的一部分的介电填料，以及由至少一组金属结构和介电填料限定的气隙区，并邻接该组金属结构的至少一部分。第二含金属层至少包括与该组金属结构的一部分电连接的通孔塞。导电焊盘和通孔插头不与气隙区域重叠。

38. 发明授权

US08334163B1 Method of forming solar cell 有权
标题翻译：形成太阳能电池的方法
公开(公告)号：US08334163B1
公开(公告)日：2012-12-18
申请号：US13439879
申请日：2012-04-05
申请人： Yen-Cheng Hu , Jen-Chieh Chen , Zhen-Cheng Wu
发明人： Yen-Cheng Hu , Jen-Chieh Chen , Zhen-Cheng Wu
IPC分类号： H01L21/00
CPC分类号： H01L21/2225 , H01L21/2254 , H01L31/022425 , H01L31/02363 , H01L31/0288 , H01L31/068 , Y02E10/547
摘要： A method of forming solar cell includes forming a doping paste on a first surface of a semiconductor substrate to form a selective emitter, to render the selective emitter a non-textured surface, and forming a texturing barrier layer on a second surface of the semiconductor substrate to render the second surface a non-textured surface.
摘要翻译：一种形成太阳能电池的方法包括在半导体衬底的第一表面上形成掺杂膏以形成选择性发射极，使选择性发射极成为非纹理表面，并在半导体衬底的第二表面上形成纹理阻挡层以使第二表面成为非纹理表面。

39. 发明申请

US20120264253A1 METHOD OF FABRICATING SOLAR CELL 审中-公开
标题翻译：制造太阳能电池的方法
公开(公告)号：US20120264253A1
公开(公告)日：2012-10-18
申请号：US13190498
申请日：2011-07-26
申请人： Ming-Hui Chiu , Shih-Hsien Yang , Yen-Cheng Hu , Yu-Chun Chen , Tsung-Pao Chen , Kuan-Chen Wang , Jen-Chieh Chen , Zhen-Cheng Wu
发明人： Ming-Hui Chiu , Shih-Hsien Yang , Yen-Cheng Hu , Yu-Chun Chen , Tsung-Pao Chen , Kuan-Chen Wang , Jen-Chieh Chen , Zhen-Cheng Wu
IPC分类号： H01L31/18
CPC分类号： H01L31/18 , H01L31/0288 , H01L31/02963 , H01L31/0323 , H01L31/068 , H01L31/1804 , H01L31/1828 , Y02E10/541 , Y02E10/543 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a solar cell is provided. A first type substrate having a first surface and a second surface is provided. A first doping process is performed on the first surface of the first type substrate by using a first dopant, so as to form a first type lightly doped layer. A second doping process is performed on a portion of the first type lightly doped layer by using a second dopant, so as to form a second type heavily doped region. A molecular weight of the second dopant is larger than a molecular weight of the first dopant, and a temperature of the first doping process is higher than a temperature of the second doping process. A first electrode is formed on the second type heavily doped region. A second electrode is formed on the second surface of the first type substrate.
摘要翻译：提供一种制造太阳能电池的方法。提供具有第一表面和第二表面的第一类型基底。通过使用第一掺杂剂在第一类型衬底的第一表面上进行第一掺杂工艺，以形成第一类型的轻掺杂层。通过使用第二掺杂剂在第一类型轻掺杂层的一部分上进行第二掺杂工艺，以形成第二类型重掺杂区域。第二掺杂剂的分子量大于第一掺杂剂的分子量，并且第一掺杂工艺的温度高于第二掺杂工艺的温度。在第二种重掺杂区域上形成第一电极。第二电极形成在第一类型基板的第二表面上。

40. 发明申请

US20110198757A1 SEMICONDUCTOR STRUCTURE HAVING AN AIR-GAP REGION AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有空气隙区域的半导体结构及其制造方法
公开(公告)号：US20110198757A1
公开(公告)日：2011-08-18
申请号：US12707969
申请日：2010-02-18
申请人： Shu-Hui SU , Cheng-Lin Huang , Jiing-Feng Yang , Zhen-Cheng Wu , Ren-Guei Wu , Dian-Hau Chen , Yuh-Jier Mll
发明人： Shu-Hui SU , Cheng-Lin Huang , Jiing-Feng Yang , Zhen-Cheng Wu , Ren-Guei Wu , Dian-Hau Chen , Yuh-Jier Mll
IPC分类号： H01L23/48 , H01L21/768 , H01L23/498 , G03F1/00
CPC分类号： H01L23/5226 , H01L21/02203 , H01L21/76805 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76834 , H01L21/76897 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.
摘要翻译：半导体结构包括第一含金属层，电介质覆盖层，第二含金属层和导电焊盘。第一含金属层包括一组金属结构，设置成占据第一含金属层的一部分的介电填料，以及由至少一组金属结构和介电填料界定的气隙区，该组金属结构的至少一部分。第二含金属层至少包括与该组金属结构的一部分电连接的通孔塞。导电焊盘和通孔插头不与气隙区域重叠。

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