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31. 发明授权

US09165917B2 In-line stacking of transistors for soft error rate hardening 有权
标题翻译：用于软错误率硬化的晶体管的在线堆叠
公开(公告)号：US09165917B2
公开(公告)日：2015-10-20
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
IPC分类号： H01L27/11 , H01L27/02 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译：一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进具有跨越两个晶体管的相对较小的立体角。这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

32. 发明申请

US20130263611A1 COOLING SYSTEM CONTROL AND SERVICING BASED ON TIME-BASED VARIATION OF AN OPERATIONAL VARIABLE 有权
公开(公告)号：US20130263611A1
公开(公告)日：2013-10-10
申请号：US13442897
申请日：2012-04-10
申请人： Daniel J. KEARNEY , Rejean P. LEVESQUE , K. Paul MULLER , Andrew H. VOGEL , Emmanuel YASHCHIN
发明人： Daniel J. KEARNEY , Rejean P. LEVESQUE , K. Paul MULLER , Andrew H. VOGEL , Emmanuel YASHCHIN
IPC分类号： F28F27/00 , G05D23/19 , F25D31/00
CPC分类号： F28F27/00 , F25B5/02 , F25B49/02 , F25B2600/2513 , F25B2700/2106 , F25B2700/21152 , F25B2700/21161 , F25B2700/21162 , F25B2700/21163 , F25B2700/21174 , F25B2700/21175 , H05K7/20836
摘要： Automated control of a cooling system cooling at least one electronic component is provided. The control includes monitoring over a period of time variation of an operational variable of the cooling system or of the at least one electronic component, and based, at least in part, on variation of the operational variable over the period of time, automatically determining whether to adjust control of the cooling system to limit variation of the operational variable. In one implementation, depending on the variation of the operational variable, and whether control of the cooling system has been previously adjusted, the method may further include automatically determining a probability of fail or an expected residual life of the cooling system, and responsive to the predicted probability of fail exceeding a first acceptable threshold or the expected residual life being below a second acceptable threshold, automatically scheduling for a cooling system repair or replacement.

33. 发明授权

US08354858B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US08354858B2
公开(公告)日：2013-01-15
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

34. 发明授权

US07888959B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US07888959B2
公开(公告)日：2011-02-15
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

35. 发明申请

US20100301446A1 IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING 有权
标题翻译：用于软错误速率硬化的晶体管的在线堆叠
公开(公告)号：US20100301446A1
公开(公告)日：2010-12-02
申请号：US12473409
申请日：2009-05-28
申请人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
发明人： Ethan H. Cannon , David F. Heidel , K. Paul Muller , Alicia Wang
IPC分类号： H01L27/12 , H01L21/28
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of “in-line” connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art “side-by-side” transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.
摘要翻译：一对CMOS晶体管中的每一个形成在其自身的岛中，并且每个晶体管的栅极端子由连接两个栅极端子的单个直列导体形成。与现有技术的“并排”晶体管堆叠通过使用相比，这种“在线”连接实现了与电离辐射颗粒同时撞击两个晶体管的能力的降低近乎五次的改进具有跨越两个晶体管的相对较小的立体角。这导致了晶体管的“硬化”，并提高了它们对单一事件的影响，从而提高了晶体管的软错误率（SER）。

36. 发明授权

US07683434B2 Preventing cavitation in high aspect ratio dielectric regions of semiconductor device 失效
标题翻译：防止半导体器件的高长宽比介电区域产生气蚀
公开(公告)号：US07683434B2
公开(公告)日：2010-03-23
申请号：US12190777
申请日：2008-08-13
申请人： Paul D. Agnello , Rajeev Malik , K. Paul Muller
发明人： Paul D. Agnello , Rajeev Malik , K. Paul Muller
IPC分类号： H01L29/76 , H01L29/94 , H01L31/119 , H01L31/062 , H01L31/113
CPC分类号： H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823425 , H01L21/823468 , H01L21/823475
摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.
摘要翻译：公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。轴承表面防止随后填充高纵横比区域的层间电介质的空化。

37. 发明授权

US06774437B2 Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication 有权
标题翻译：基于鳍的双重多晶硅动态阈值CMOS FET与间隔栅极和制造方法
公开(公告)号：US06774437B2
公开(公告)日：2004-08-10
申请号：US09683486
申请日：2002-01-07
申请人： Andres Bryant , K. Paul Muller , Edward J. Nowak
发明人： Andres Bryant , K. Paul Muller , Edward J. Nowak
IPC分类号： H01L2704
CPC分类号： H01L29/785 , H01L21/2815 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795 , H01L29/783
摘要： The present invention provides a dynamic threshold (DT) CMOS FET and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a DT CMOS FET with a short, low resistance connection between the gate and the body and with low body-to-source/drain capacitance. The low body-to-source/drain capacitance is achieved using a thin, fin-type body. The low resistance connection between the gate and the body contact is achieved by having the gate and body contact aligned on opposite long sides of the fin with a bridge over the top of the narrow fin electrically connecting the gate and body.
摘要翻译：本发明提供一种动态阈值（DT）CMOS FET及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了一种DT CMOS FET，其在栅极和主体之间具有短的低电阻连接，并且具有低的体/源极/漏极电容。使用薄的鳍式体实现了较低的体源对漏极电容。栅极和体接触之间的低电阻连接是通过使栅极和主体接触在翅片的相对的长边上对准来实现的，桥与电极连接门和主体的窄鳍的顶部之间形成桥。

38. 发明授权

US6140833A In-situ measurement method and apparatus for semiconductor processing 有权
标题翻译：用于半导体处理的现场测量方法和装置
公开(公告)号：US6140833A
公开(公告)日：2000-10-31
申请号：US192698
申请日：1998-11-16
申请人： Bertrand Flietner , K. Paul Muller
发明人： Bertrand Flietner , K. Paul Muller
IPC分类号： G05B19/00 , G05D23/00 , H01L21/66 , H01L23/544 , G01R31/00
CPC分类号： B24B37/013 , H01L22/26 , H01L22/34
摘要： A measurement device for in-situ measurement of processing parameters, in accordance with the present invention, includes a semiconductor wafer having at least one processed chip formed thereon. The processed chip further includes at least one sensor for measuring process parameters. A memory storage device for storing the process parameters as the process parameters are measured by the at least one sensor is also included. A timing device is provided for tracking the process parameters as a function of time, and a power supply is included for providing power to the at least one sensor, the memory storage device and the timing device. Also, a method is described for making measurements with the measurement device.
摘要翻译：根据本发明的用于原位测量处理参数的测量装置包括其上形成有至少一个处理的芯片的半导体晶片。处理后的芯片还包括至少一个用于测量工艺参数的传感器。还包括用于存储作为处理参数的处理参数的存储器存储装置，其由至少一个传感器测量。提供了一种定时装置，用于跟踪作为时间的函数的过程参数，并且包括用于向至少一个传感器，存储器存储装置和定时装置提供电力的电源。另外，描述了使用测量装置进行测量的方法。

39. 发明授权

US5956142A Method of end point detection using a sinusoidal interference signal for a wet etch process 失效
标题翻译：使用用于湿式蚀刻工艺的正弦干涉信号的端点检测方法
公开(公告)号：US5956142A
公开(公告)日：1999-09-21
申请号：US937572
申请日：1997-09-25
申请人： K. Paul Muller , Klaus Dieter Penner
发明人： K. Paul Muller , Klaus Dieter Penner
IPC分类号： C23F1/00 , G01B11/06 , H01L21/306 , G01B9/02
CPC分类号： G01B11/0683
摘要： A process for monitoring and determining the end point of a wet etch process for removing a thin solid film 116 from a substrate by directing a light beam onto the substrate and monitoring the intensity of reflected beams, including the step of selecting a coherence length of the incoming beam 120 so that it is small enough so that no interference occurs in the liquid layer and large enough so that interference can occur in the thin solid film, i.e., light reflected from the interface between the liquid 118 and the top of the thin film, and light reflected from the interface between the bottom of the thin solid film and the substrate interferes. If the liquid layer is about 100 micrometers thick, and the thin film is about 1 micrometer thick, a coherence length of about 10 micrometers is suitable. Such coherence length can be provided with a suitable bandpass filter.
摘要翻译：一种用于监测和确定湿式蚀刻工艺的终点的方法，用于通过将光束引导到衬底上并监测反射光束的强度来从衬底去除薄的固体膜116，包括选择相干长度的步骤进入光束120使其足够小，使得在液体层中不会发生干扰并且足够大，使得在薄的固体膜中可能发生干扰，即从液体118和薄膜的顶部之间的界面反射的光并且从薄固体膜的底部与基板之间的界面反射的光干涉。如果液体层的厚度约为100微米，薄膜的厚度约为1微米，则约10微米的相干长度是合适的。这种相干长度可以提供合适的带通滤波器。

40. 发明授权

US5891807A Formation of a bottle shaped trench 失效
标题翻译：形成一个瓶形沟槽
公开(公告)号：US5891807A
公开(公告)日：1999-04-06
申请号：US937526
申请日：1997-09-25
申请人： K. Paul Muller , Rajiv M. Ranade , Stefan Schmitz
发明人： K. Paul Muller , Rajiv M. Ranade , Stefan Schmitz
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/8242 , H01L27/108 , H01L21/306 , B44C1/22 , C03C25/06
CPC分类号： H01L21/3065
摘要： A method for forming a bottle shaped trench 20 in a semiconductor substrate 10 includes reactive ion etching a trench having a tapered top portion 25 in the semiconductor device and continuing to reactive ion etch while increasing the temperature of the semiconductor device to impart a reentrant profile 22 to the trench.
摘要翻译：在半导体衬底10中形成瓶形沟槽20的方法包括在半导体器件中具有锥形顶部25的沟槽的反应离子蚀刻，并且继续进行反应离子蚀刻，同时增加半导体器件的温度以赋予折入轮廓22 到沟渠

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