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21. 发明授权

US4692891A Coded decimal non-restoring divider 失效
标题翻译：编码十进制非恢复分频器
公开(公告)号：US4692891A
公开(公告)日：1987-09-08
申请号：US668842
申请日：1984-11-06
申请人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama
发明人： Akira Yamaoka , Kenichi Wada , Kazunori Kuriyama
IPC分类号： G06F7/496 , G06F7/491 , G06F7/493 , G06F7/508 , G06F7/52 , G06F7/535 , G06F7/537
CPC分类号： G06F7/4917
摘要： This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division.A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively.The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.
摘要翻译：本发明采用并行执行十进制除法中的减法处理和数位移位处理以缩短小数除法所需的时间的结构。在寄存器C中将寄存器B和除数存储除数。当加法器/减法器1的减法结果为正或0时，选择器6选择寄存器B，并且在其他时间选择寄存器A. 加法器/减法器1和移位器2以相同的方式接收来自选择器6的信号，并分别执行减法处理和移位处理。这些处理的结果分别存储在寄存器B和A'中。由于可以同时启动加法器/减法器1和移位器2，所以可以缩短分频时间。

22. 发明授权

US4384341A Data processor having carry apparatus supporting a decimal divide operation 失效
标题翻译：具有支持小数除法运算的进位装置的数据处理器
公开(公告)号：US4384341A
公开(公告)日：1983-05-17
申请号：US219638
申请日：1980-12-24
申请人： Steven A. Tague , Virendra S. Negi
发明人： Steven A. Tague , Virendra S. Negi
IPC分类号： G06F7/496 , G06F7/483 , G06F7/491 , G06F7/493 , G06F7/508 , G06F7/52 , G06F7/533
CPC分类号： G06F7/4917
摘要： A commercial instruction processor executes a decimal divide instruction by counting the number of subtractions by the divisor resulting in a positive remainder to develop the quotient. Apparatus compares the most significant decimal digit of the divisor with the most significant decimal digit of the remainder after each subtraction pass to predict if the next subtraction pass would result in a negative remainder. If so, a quotient decimal digit is stored in a memory, the divisor is shifted one decimal digit position to the right, and a series of subtraction passes are made to develop the next quotient decimal digit.
摘要翻译：商业指令处理器通过对由除数产生的正数余数进行计数来执行十进制除法指令来开发商。设备将除数的最有意义的十进制数与每次减法通过后余数中最有效的十进制数进行比较，以预测下一个减法通过是否会导致负余数。如果是这样的话，一个商数十进制数存储在一个存储器中，除数将一个十进制数位置向右移位，并进行一系列的减法遍数来形成下一个十进制数字。

23. 发明授权

US4138731A High speed binary and binary coded decimal adder 失效
标题翻译：高速二进制和二进制编码十进制加法器
公开(公告)号：US4138731A
公开(公告)日：1979-02-06
申请号：US859184
申请日：1977-12-09
申请人： Shigemi Kamimoto , Toshio Hayashi , Kazuyuki Shimizu
发明人： Shigemi Kamimoto , Toshio Hayashi , Kazuyuki Shimizu
IPC分类号： G06F7/493 , G06F7/494 , G06F7/50 , G06F7/508
CPC分类号： G06F7/494 , G06F7/508 , G06F2207/4924
摘要： A high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a binary coded decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and binary coded decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages.
摘要翻译：一种高速二进制和二进制编码十进制加法器，其采用多个部分加法器和进位查看提前电路，并且适于仅通过加法器的一个处理来实现二进制编码的十进制加法。部分加法器由半加法器构成，用于产生位产生信号和位传播信号，二进制模式携带前瞻输入信号发生器电路部分，二进制编码十进制进位前瞻输入信号发生器电路部分，中间加法器部分和全加器部分。高速二进制和二进制编码十进制加法器能够以对应于六到七个逻辑级的速度提供加法结果。

24. 发明授权

US4110831A Method and means for tracking digit significance in arithmetic operations executed on decimal computers 失效
标题翻译：用于在十进制计算机上执行的算术运算中跟踪数字含义的方法和手段
公开(公告)号：US4110831A
公开(公告)日：1978-08-29
申请号：US811214
申请日：1977-06-29
申请人： Glen G. Langdon, Jr.
发明人： Glen G. Langdon, Jr.
IPC分类号： G06F7/38 , G06F7/00 , G06F7/483 , G06F7/493 , G06F7/494 , G06F7/50 , G06F7/506
CPC分类号： G06F7/494 , G06F2207/4911 , G06F2207/4924 , G06F7/49963
摘要： Method and means are described for the tracking of digit significance upon operands arithmetically combined in a series of binary operations such as addition, subtraction, or shifting in a decimal computer. The digits are decimally encoded in a format having enough excess capacity such that nonsignificant digits are unique. As part of the arithmetic combining of the operand, pairs of digits of like order but possibly mismatched as to significance and by observing a predetermined rounding rule may also cause a carry value to be propagated to a digit position of higher order. In subtraction by complement addition, an additional carry is propagated to a higher order position conditioned upon there being either a local overflow, a nonsignificant subtrahend, or a nonsignificant minuend and a subtrahend less than an amount specified by a rounding rule. Between the two operands, this results in the rounding of the more precise operand to the least significant digit position of the less precise operand. The method and means are applicable to floating point, sign plus magnitude, radix and diminished radix complement number representation forms.
摘要翻译：描述了用于在诸如加法，减法或十进制计算机中的移位的一系列二进制操作中算术组合的操作数上跟踪数字重要性的方法和装置。数字以具有足够的额外容量的格式进行十进制编码，使得非有效数字是唯一的。作为操作数的算术组合的一部分，类似顺序的数字对，但是可能与重要性不匹配，并且通过观察预定的舍入规则，也可以使进位值传播到高阶数位置。在通过补数相加的减法中，附加进位被传播到较高阶位置，该高阶位置被调节为存在局部溢出，非重要的减数或非显着的下降以及小于由舍入规则指定的量的减数。在两个操作数之间，这导致将更精确的操作数舍入到较不精确的操作数的最低有效数字位置。方法和手段适用于浮点，符号加大小，基数和减数补数补码数表示形式。

25. 发明授权

US4001570A Arithmetic unit for a digital data processor 失效
标题翻译：数字数据处理器的算术单元
公开(公告)号：US4001570A
公开(公告)日：1977-01-04
申请号：US587797
申请日：1975-06-17
申请人： David N. Gooding , Everett M. Shimp
发明人： David N. Gooding , Everett M. Shimp
IPC分类号： G06F7/48 , G06F7/493 , G06F7/494 , G06F7/50 , G06F7/508 , G06F7/385
CPC分类号： G06F7/494 , G06F2207/4924
摘要： A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values. The input modifier circuitry for one of the numbers also includes circuitry for increasing the value of each digit in such number by a factor of six for enabling the proper generation of digit carries inside the binary adder. The output corrector includes circuitry for reducing, when necessary, the value of one or more of the output digits by a factor of six to offset the increase in the input digits. Subtraction is accomplished by complementing one of the numbers before it is supplied to the binary adder. Sign handling circuitry detects the polarities or signs of the two input numbers as well as the status of an external add/subtract command and processes these three factors to develop a control signal for controlling the use of the complementing action for enabling the number appearing at the output of the output corrector to be in true magnitude form whenever possible. The input modifier circuitry, the output corrector and the sign handling circuitry are constructed so that packed binary coded decimal numbers and pure binary numbers can also be handled by the arithmetic unit.

26. 发明授权

US3997765A Circulating shift register incrementer/decrementer 失效
标题翻译：循环移位寄存器递增器/递减器
公开(公告)号：US3997765A
公开(公告)日：1976-12-14
申请号：US595655
申请日：1975-07-14
申请人： Vijay V. Marathe
发明人： Vijay V. Marathe
IPC分类号： G04G99/00 , G06F7/493 , G06F7/504 , G06F7/508 , G11C19/00 , H03K27/00
CPC分类号： H03K27/00
摘要： The circulating shift register time-keeping circuit described herein includes an incrementer/decrementer that increments and decrements the contents of both clock and stopwatch registers and performs reset and carry functions therefor.
摘要翻译：本文描述的循环移位寄存器保持电路包括递增器/递减器，其递增和递减时钟和秒表寄存器的内容，并执行复位和携带功能。

27. 发明授权

US3816728A Modulo 9 residue generating and checking circuit 失效
标题翻译： MODULO 9残留产生和检查电路
公开(公告)号：US3816728A
公开(公告)日：1974-06-11
申请号：US31526872
申请日：1972-12-14
申请人： IBM
发明人： CHEN T , HO I
IPC分类号： G06F7/38 , G06F7/00 , G06F7/493 , G06F7/499 , G06F11/10
CPC分类号： G06F11/104
摘要： A modulo 9 residue generating and checking circuit for checking the accuracy of decimal addition operations in digital computers and other data processing equipment. A set of data words each representing a number to be added is transmitted to a multinumber adder which adds the words and provides a smaller set of words as a subtotal sum. The bits of the subtotal words are then divided into two groups. Each group of bits is fed to a respective modulo 9 residue generator which calculates the modulo 9 residue of the group. The two resulting residues are then fed to a third modulo 9 residue generator which calculates the modulo 9 residue of the sum of the two residues, thereby providing the modulo 9 residue of the sum of the original set of data words. This result may then be compared in the conventional manner with the modulo 9 residue of the sum resulting from the addition operation to be checked.
摘要翻译：一种用于检查数字计算机和其他数据处理设备中十进制加法运算精度的模9残差生成和检查电路。将表示要添加的数字的一组数据字发送给多位加法器，该多位加法器相加字并提供较小的一组单词作为小计和。然后将小计字的位分成两组。每组比特被馈送到相应的模9残差生成器，其计算组的模9残差。然后将得到的两个残差送入第三个模9残差生成器，该第三个模9残差生成器计算两个残差之和的模9个残差，从而提供原始数据集合的和的模9残差。然后将该结果以常规方式与由待检查的相加操作产生的总和的模9残差进行比较。

28. 发明授权

US3775601A Arithmetic system for use in electronic calculator 失效
标题翻译：用于电子计算机的算术系统
公开(公告)号：US3775601A
公开(公告)日：1973-11-27
申请号：US3775601D
申请日：1971-11-30
申请人： OMRON TATEISI ELECTRONICS CO
发明人： HATANO I , NAGANO A
IPC分类号： G06F7/38 , G06F7/493 , G06F7/525 , G06F15/02
CPC分类号： G06F15/02
摘要： An arithmetic system for use in an electronic calculator including an additional register for storing a constant number which is used in an arithmetic calculation such as division, subtraction, addition and multiplication with respect to a series of arbitrary numbers. The content stored in the additional register is utilized only when the constant calculation is to be performed.
摘要翻译：一种用于电子计算器的算术系统，包括用于存储用于关于一系列任意数字的除法，减法，加法和乘法的算术计算中的常数的附加寄存器。存储在附加寄存器中的内容仅在执行常数计算时才被使用。

29. 发明授权

US5638314A Dividing apparatus for use in a data processing apparatus 失效
标题翻译：用于数据处理装置的分割装置
公开(公告)号：US5638314A
公开(公告)日：1997-06-10
申请号：US329317
申请日：1994-10-26
申请人： Yuji Yoshida
发明人： Yuji Yoshida
IPC分类号： G06F7/491 , G06F7/493 , G06F7/496 , G06F7/52 , G06F7/53
CPC分类号： G06F7/4917
摘要： A dividing apparatus which allows settlement of a quotient of one digit with a simple circuit construction is disclosed. A plurality of different integer multiples are simultaneously subtracted individually from a dividend or an intermediate remainder, and when all of results of the subtraction are in the negative in sign, the dividend or intermediate remainder before the subtraction is selected as it is as a new intermediate remainder, but when some or all of the results of the subtraction are in the positive in sign or zero, that one of those results of the subtraction having the positive sign or the value of zero which corresponds to a highest one of the multiples is selected as a new intermediate remainder, whereafter the states of carry signals corresponding to the results of the subtraction are held. A processing cycle of the operations is repetitively executed by a plurality of times, and then a quotient is calculated in accordance with the held states of the carry signals. The dividing apparatus can be applied to division of a dividend by a divisor both in the form of decimal data in binary-coded decimal notation.
摘要翻译：公开了一种能够以简单的电路结构结算一位数的商的分割装置。从分红或中间余数中分别同时减去多个不同的整数倍，并且当所有减法结果在符号中为负时，减法前的除数或中间余数作为新的中间值被选择但是当减法的某些或全部结果在符号或零中为正时，选择具有正符号或相应于该倍数中最高的一个的零值的那些减法结果中的一个被选择作为新的中间余数，之后保持与减法结果相对应的进位信号的状态。操作的处理周期被多次重复执行，然后根据进位信号的保持状态来计算商。分割装置可以应用于由二进制编码十进制表示的十进制数据形式的除数除数的除数。

30. 发明授权

US5029069A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US5029069A
公开(公告)日：1991-07-02
申请号：US171581
申请日：1988-03-22
申请人： Ken Sakamura
发明人： Ken Sakamura
IPC分类号： G06F7/38 , G06F7/483 , G06F7/493 , G06F7/508 , G06F9/302 , G06F9/305 , G06F9/32 , G06F9/00
CPC分类号： G06F9/3001 , G06F9/30094
摘要： A data processor which has instructions of operation and comparison when including the signed binary number represented by complement on 2 as the object and has a flag correctly representing the result of the operation as positive or negative regardless of whether or not overflow occurs so as to correlate the arithmetic operation close with a status flag change, thereby facilitating mathematical interpretation of the result of the operation.
摘要翻译：一种数据处理器，当将包含由2表示的带符号二进制数作为对象并具有正确表示操作结果的标志时，具有操作和比较的指令，而不管是否发生溢出以便相关联算术运算与状态标志变化关闭，从而便于操作结果的数学解释。

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