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1. 发明授权

US3999052A Upper bounds address checking system for providing storage protection for a digital data processor 失效
标题翻译：上限地址检查系统，用于为数字数据处理器提供存储保护
公开(公告)号：US3999052A
公开(公告)日：1976-12-21
申请号：US587936
申请日：1975-06-18
申请人： David N. Gooding , Everett M. Shimp
发明人： David N. Gooding , Everett M. Shimp
IPC分类号： G06F7/00 , G06F11/30 , G06F12/14 , G06F7/385 , G11C8/00
CPC分类号： G06F12/1441
摘要： Data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle and employing an independent zone parallel type arithmetic unit capable of simultaneously performing independent arithmetic operations in the different zones thereof. Data transfer circuitry is provided for immediately supplying the output result of a first arithmetic unit zone back to the input of a second arithmetic unit zone for immediately producing a second and different result. Such transfer circuitry is constructed to operate in an asynchronous manner so that the first result is supplied back to the input of the second arithmetic unit zone as soon as it becomes available at the output of the first arithmetic zone. Thus, a second result, which is dependent on the first result, is produced during the same machine control cycle as the first result. This data processing circuitry is particularly useful for providing storage protection for a data processor. In such case, the current storage address and a requested storage access length value are supplied to the first arithmetic unit zone for producing a new address representing the upper extent of the storage access request. The resultant new address is immediately supplied back to the input of the second arithmetic unit zone for combining same with an upper limit address for immediately producing an upper bounds extent error when the new address exceeds the upper limit address.
摘要翻译：数据处理电路，用于在同一机器控制周期内执行两个串行相关的算术运算，并采用能够在其不同区域中同时执行独立算术运算的独立区域并行运算单元。提供数据传送电路，用于立即将第一运算单元区域的输出结果提供给第二运算单元区域的输入，以立即产生第二和不同的结果。这种传送电路被构造成以异步方式操作，使得第一结果一旦在第一算术区的输出处可用就被提供回第二运算单元区的输入。因此，取决于第一结果的第二结果是在与第一结果相同的机器控制周期期间产生的。该数据处理电路对于为数据处理器提供存储保护特别有用。在这种情况下，将当前存储地址和请求的存储访问长度值提供给第一运算单元区，以产生表示存储访问请求的较高范围的新地址。所得到的新地址立即被提供给第二运算单元区域的输入，以将其与上限地址组合，以在新地址超过上限地址时立即产生上限范围误差。

2. 发明授权

US3986015A Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection 失效
标题翻译：用于数字数据处理器的算术单元，具有用于奇偶校验位产生和错误检测的改进系统
公开(公告)号：US3986015A
公开(公告)日：1976-10-12
申请号：US589298
申请日：1975-06-23
申请人： David N. Gooding , Everett M. Shimp
发明人： David N. Gooding , Everett M. Shimp
IPC分类号： G06F7/00 , G06F7/38 , G06F7/492 , G06F7/494 , G06F7/508 , G06F11/10 , H03M13/00 , H03K13/34 , H04L1/10
CPC分类号： G06F11/10 , G06F7/00
摘要： A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.
摘要翻译：一种采用二进制加法器的数字运算单元，用于以分区格式或打包格式对多位二进制编码十进制数进行加法和减法，并且具有为运算单元产生的结果数据字节产生奇偶校验位的改进方法。当使用二进制加法器对二进制编码十进制数进行加法或减法时，需要校正出现在二进制加法器的输出端的一些数据，以获得正确的结果。然而，本发明的奇偶校验位产生电路对于出现在加法器的输出端的未校正数据起作用，但是对于表示算术单元的最终输出的校正数据产生适当的奇偶校验位。这减少了以常规方式生成奇偶校验位的另外时间延迟的量。

3. 发明授权

US4001570A Arithmetic unit for a digital data processor 失效
标题翻译：数字数据处理器的算术单元
公开(公告)号：US4001570A
公开(公告)日：1977-01-04
申请号：US587797
申请日：1975-06-17
申请人： David N. Gooding , Everett M. Shimp
发明人： David N. Gooding , Everett M. Shimp
IPC分类号： G06F7/48 , G06F7/493 , G06F7/494 , G06F7/50 , G06F7/508 , G06F7/385
CPC分类号： G06F7/494 , G06F2207/4924
摘要： A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values. The input modifier circuitry for one of the numbers also includes circuitry for increasing the value of each digit in such number by a factor of six for enabling the proper generation of digit carries inside the binary adder. The output corrector includes circuitry for reducing, when necessary, the value of one or more of the output digits by a factor of six to offset the increase in the input digits. Subtraction is accomplished by complementing one of the numbers before it is supplied to the binary adder. Sign handling circuitry detects the polarities or signs of the two input numbers as well as the status of an external add/subtract command and processes these three factors to develop a control signal for controlling the use of the complementing action for enabling the number appearing at the output of the output corrector to be in true magnitude form whenever possible. The input modifier circuitry, the output corrector and the sign handling circuitry are constructed so that packed binary coded decimal numbers and pure binary numbers can also be handled by the arithmetic unit.

4. 发明授权

US3987291A Parallel digital arithmetic device having a variable number of independent arithmetic zones of variable width and location 失效
标题翻译：具有可变数量的可变宽度和位置的独立运算区域的并行数字运算器件
公开(公告)号：US3987291A
公开(公告)日：1976-10-19
申请号：US573656
申请日：1975-05-01
申请人： David N. Gooding , Everett M. Shimp
发明人： David N. Gooding , Everett M. Shimp
IPC分类号： G06F7/505 , G06F7/50 , G06F7/508
CPC分类号： G06F7/508 , G06F9/30036 , G06F2207/3816 , G06F2207/3828
摘要： A carry look-ahead parallel digital adder having a relatively wide overall data flow width and a pair of automatically adjustable boundary mechanisms for subdividing the adder into plural independent operating zones of variable width and variable location. Anywhere from one to three independent zones may be obtained. Independent external carry-in and carry-out lines are provided for each zone and the connecting points for such lines are automatically shifted in step with the movement of the zone boundaries.
摘要翻译：具有相对宽的总体数据流宽度的进位先行并行数字加法器和一对可自动调节的边界机制，用于将加法器分为多个可变宽度和可变位置的独立操作区域。可以从一个到三个独立区域。为每个区域提供独立的外部进位输出线，并且这些线路的连接点随着区域边界的移动而自动移位。

5. 发明授权

US4580265A Failure detection method and apparatus 失效
标题翻译：故障检测方法及装置
公开(公告)号：US4580265A
公开(公告)日：1986-04-01
申请号：US509699
申请日：1983-06-30
申请人： David N. Gooding , Stefan P. Jackowski , James T. Moyer , James W. Plant, III
发明人： David N. Gooding , Stefan P. Jackowski , James T. Moyer , James W. Plant, III
IPC分类号： H04L1/00 , G06F11/10
CPC分类号： G06F11/10
摘要： A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.
摘要翻译：故障检测装置检测电路中是否存在异常电路状况，该电路使随后发送的数据字节相对于先前发送的数据字节从一个集成电路发送到另一个集成电路。偶数和奇数数据字节由具有奇校验的第一集成电路接收。然而，偶数数据字节从具有奇数奇偶校验的集成电路之间沿现有接口线传输从第一集成电路传输到第二集成电路。奇数数据字节的奇偶校验位反转，奇数数据字节沿现有的接口线以偶校验发送。第二集成电路中的异或门接收偶数数据字节的奇偶校验位，并响应于来自奇数锁存器的时钟信号的第一状态而不反转地通过奇偶校验位; 然而，异或门在接收到奇数数据字节时响应于时钟信号的第二状态重新反转奇数数据字节的奇偶校验位。奇偶校验器将输入偶数和奇数数据字节的数据位与异或门产生的奇偶校验位进行比较，并产生一个错误检查信号，代表随后发送的数据字节的接收，该序列相对于先前传输当奇偶检验器的输入端的数据位和奇偶校验位的组合奇偶校验不是奇数时的数据字节。

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