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21. 发明申请

US20050036376A1 Magnetic random access memory 审中-公开
标题翻译：磁性随机存取存储器
公开(公告)号：US20050036376A1
公开(公告)日：2005-02-17
申请号：US10945139
申请日：2004-09-21
申请人： Yoshihisa Iwata , Tomoki Higashi
发明人： Yoshihisa Iwata , Tomoki Higashi
IPC分类号： G11C11/15 , G11C11/16 , G11C11/00
CPC分类号： G11C11/16 , G11C11/15
摘要： TMR elements are arranged at the intersections between word lines and bit lines. One end of each word line is connected to the ground point through a row select switch. One end of each bit line is connected to a bit line bias circuit. In read operation, the bit line bias circuit applies a bias potential to all the bit lines. The selected word line is short-circuited to the ground point. Unselected word lines are set in a floating state.
摘要翻译： TMR元件布置在字线和位线之间的交点处。每个字线的一端通过行选择开关连接到地面点。每个位线的一端连接到位线偏置电路。在读操作中，位线偏置电路向所有位线施加偏置电位。所选字线短路到地面点。未选择的字线设置为浮动状态。

22. 发明申请

US20050030785A1 Magnetic random access memory 失效
公开(公告)号：US20050030785A1
公开(公告)日：2005-02-10
申请号：US10939415
申请日：2004-09-14
申请人： Yoshihisa Iwata
发明人： Yoshihisa Iwata
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/16 , G11C2207/2263
摘要： In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.

23. 发明授权

US06625057B2 Magnetoresistive memory device 失效
公开(公告)号：US06625057B2
公开(公告)日：2003-09-23
申请号：US09985587
申请日：2001-11-05
申请人： Yoshihisa Iwata
发明人： Yoshihisa Iwata
IPC分类号： G11C1100
CPC分类号： G11C11/5607 , B82Y10/00 , G11C11/15
摘要： An integrated semiconductor memory device with an array of memory cells MC using magnetic tunnel junction (MTJ) cells is disclosed. A sense amplifier SA that is connected to a bit line BL for data readout of a selected memory cell MC is arranged using an operational amplifier OP. The operational amplifier OP has an inverting input terminal which is connected to the bit line BL and a non-inverting input terminal, to which a potentially fixed constant voltage VC is given. A PMOS transistor Q31 is provided, which can also do double-duty as a current source load. This PMOS transistor has its drain and gate that are connected to the inverting input terminal, and a source as connected to an output terminal of the operational amplifier OP whereby the transistor is under feedback control in response to an output of the operational amplifier OP so that a clamped voltage potential of the bit lime BL is fixed to the voltage VC.

24. 发明授权

US06590444B2 Semiconductor integrated circuit with a down converter for generating an internal voltage 失效
标题翻译：具有用于产生内部电压的降压转换器的半导体集成电路
公开(公告)号：US06590444B2
公开(公告)日：2003-07-08
申请号：US10200152
申请日：2002-07-23
申请人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
发明人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
IPC分类号： G05F302
CPC分类号： G05F1/465
摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.
摘要翻译：为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。此外，通过在待机模式中采用PMOS下变频器和在活动模式中的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置处于待机模式的PMOS下变频器的内部电源电压高于活动模式。下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离电源电压最小化，内部电源电压的可控性提高。

25. 发明授权

US6081454A Electrically erasable programmable read-only memory with threshold value controller for data programming 失效
标题翻译：电可擦除可编程只读存储器，具有用于数据编程的阈值控制器
公开(公告)号：US6081454A
公开(公告)日：2000-06-27
申请号：US145466
申请日：1998-09-02
申请人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
发明人： Kazunori Ohuchi , Tomoharu Tanaka , Yoshihisa Iwata , Yasuo Itoh , Masaki Momodomi , Fujio Masuoka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/26 , G11C16/34 , G11C29/00 , G11C29/12 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3454
摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.
摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。当在数据编程模式下将数据一次写入所选择的存储单元中时，将特定的偏置电压施加到所选择的单元，从而验证所选存储单元的实际电数据写入状态。如果比较器检测到验证的写入条件不满意，则通过向所选择的单元格额外提供补偿所选择的存储单元晶体管中的验证的写入条件的不满足的适当电压来重复执行数据重写操作。

26. 发明授权

US6023424A Nonvolatile semiconductor memory device having verify function 有权
公开(公告)号：US6023424A
公开(公告)日：2000-02-08
申请号：US213411
申请日：1998-12-17
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

27. 发明授权

US5880994A Non-volatile semiconductor memory device having verify function 失效
标题翻译：具有验证功能的非易失性半导体存储器件
公开(公告)号：US5880994A
公开(公告)日：1999-03-09
申请号：US909727
申请日：1997-08-12
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line and line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，晶体管对位线和线进行充电。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与在验证模式之前的状态。

28. 发明授权

US5818791A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5818791A
公开(公告)日：1998-10-06
申请号：US826152
申请日：1997-03-27
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

29. 发明授权

US5724300A Non-volatile semiconductor memory device and memory system using the same 失效
公开(公告)号：US5724300A
公开(公告)日：1998-03-03
申请号：US784927
申请日：1997-01-16
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G06F11/10 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/34 , G11C29/00 , G11C29/34 , G11C29/52 , G11C13/00
CPC分类号： G11C29/785 , G06F11/1008 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52 , G06F11/1068 , G06F2201/81 , G06F2212/2022
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

30. 发明授权

US5508957A Non-volatile semiconductor memory with NAND cell structure and switching transistors with different channel lengths to reduce punch-through 失效
标题翻译：具有NAND单元结构的非易失性半导体存储器和具有不同通道长度的开关晶体管以减少穿通
公开(公告)号：US5508957A
公开(公告)日：1996-04-16
申请号：US312072
申请日：1994-09-26
申请人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
发明人： Masaki Momodomi , Fujio Masuoka , Yasuo Itoh , Hiroshi Iwahashi , Yoshihisa Iwata , Masahiko Chiba , Satoshi Inoue , Riichiro Shirota , Ryozo Nakayama , Kazunori Ohuchi , Shigeyoshi Watanabe , Ryouhei Kirisawa
IPC分类号： G11C16/04 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/115 , G11C16/06 , H01L29/788
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/10 , G11C16/16 , H01L27/115
摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.
摘要翻译：具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管晶体管和地。每个单元晶体管具有浮置栅极和控制栅极。字线连接到单元晶体管的控制栅极。在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元。用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

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