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1. 发明授权

US06351179B1 Semiconductor integrated circuit having active mode and standby mode converters 有权
标题翻译：具有主动模式和待机模式转换器的半导体集成电路
公开(公告)号：US06351179B1
公开(公告)日：2002-02-26
申请号：US09375370
申请日：1999-08-17
申请人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
发明人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.
摘要翻译：为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。此外，通过在待机模式中采用PMOS下变频器和在激活模式下的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置处于待机模式的PMOS下变频器的内部电源电压高于活动模式。下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离电源电压最小化，内部电源电压的可控性提高。

2. 发明授权

US06590444B2 Semiconductor integrated circuit with a down converter for generating an internal voltage 失效
标题翻译：具有用于产生内部电压的降压转换器的半导体集成电路
公开(公告)号：US06590444B2
公开(公告)日：2003-07-08
申请号：US10200152
申请日：2002-07-23
申请人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
发明人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
IPC分类号： G05F302
CPC分类号： G05F1/465
摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.
摘要翻译：为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。此外，通过在待机模式中采用PMOS下变频器和在活动模式中的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置处于待机模式的PMOS下变频器的内部电源电压高于活动模式。下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离电源电压最小化，内部电源电压的可控性提高。

3. 发明授权

US06801060B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06801060B2
公开(公告)日：2004-10-05
申请号：US10443820
申请日：2003-05-23
申请人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
发明人： Tamio Ikehashi , Yoshihisa Sugiura , Kenichi Imamiya , Ken Takeuchi , Yoshihisa Iwata
IPC分类号： H03K5153
CPC分类号： G05F1/465
摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.
摘要翻译：为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。此外，通过在待机模式中采用PMOS下变频器和在活动模式中的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置处于待机模式的PMOS下变频器的内部电源电压高于活动模式。下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离电源电压最小化，内部电源电压的可控性提高。

4. 发明授权

US5388084A Non-volatile semiconductor memory device with high voltage generator 失效
标题翻译：具有高压发生器的非易失性半导体存储器件
公开(公告)号：US5388084A
公开(公告)日：1995-02-07
申请号：US128087
申请日：1993-09-29
申请人： Yasuo Itoh , Sumio Tanaka , Junichi Miyamoto , Hiroshi Nakamura , Yoshihisa Iwata , Kenichi Imamiya , Yoshihisa Sugiura
发明人： Yasuo Itoh , Sumio Tanaka , Junichi Miyamoto , Hiroshi Nakamura , Yoshihisa Iwata , Kenichi Imamiya , Yoshihisa Sugiura
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C5/147 , G11C16/30
摘要： Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.
摘要翻译：公开了一种半导体集成电路装置，其包括用于升压源极电压的升压电路，具有连接到升压电路的输出端子的一端的限压器，用于将升压电路的输出电压限制在给定值，以及连接到限压器的另一端的电压设定电路，用于任意地调节限压器另一端的电压。该设计可以将升压电路的输出电压保持在恒定电平，并可将该输出电压设置为任意电压。

5. 发明授权

US5986929A Multi-level nonvolatile semiconductor memory device 失效
标题翻译：多级非易失性半导体存储器件
公开(公告)号：US5986929A
公开(公告)日：1999-11-16
申请号：US80250
申请日：1998-05-18
申请人： Yoshihisa Sugiura , Tamio Ikehashi
发明人： Yoshihisa Sugiura , Tamio Ikehashi
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642
摘要： The threshold voltage distribution for write operation into memory cells of a multi-level nonvolatile semiconductor memory device is precisely controlled and the verify result of written data is simultaneously detected for each page. For example, at the "10" data write time, excess write of "00" data which is a conventional problem is inhibited by controlling a path for transferring a lower bit to a bit line according to an upper bit. Further, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the upper bit. At the write time of "01" data, the bit line path is controlled by use of the lower bit and the write operation of "00" data is inhibited. Also, at the write-verify time, the verify result can be simultaneously detected for each page by controlling the verify operation according to the lower bit. The write and verify operations of "00" data can be effected in the same manner as in the case of "01" data by first inverting the lower bit of "00" data. Since the write operation can be effected while all of the write states of a plurality of bits are verified, each level of written data can be precisely controlled without causing excess or insufficiency in the threshold voltage after the write operation into the memory cell. Further, since the verify result can be simultaneously detected for each page, time can be significantly reduced.
摘要翻译：对多级非易失性半导体存储器件的存储单元进行写操作的阈值电压分布被精确地控制，并且每一页同时检测写入数据的验证结果。例如，在“10”数据写入时，通过根据高位控制用于将较低位传送到位线的路径来禁止作为常规问题的“00”数据的超量写入。此外，在写入验证时间，通过根据高位控制验证操作，可以对每个页面同时检测验证结果。在“01”数据的写入时间，通过使用低位来控制位线路径，并且禁止“00”数据的写入操作。此外，在写验证时间，通过根据较低位控制验证操作，可以对每一页同时检测验证结果。 “00”数据的写入和验证操作可以通过首先反转“00”数据的较低位，以与“01”数据相同的方式进行。由于可以在多个位的所有写入状态都被验证的同时进行写入操作，所以可以精确地控制每个级别的写入数据，而不会在对存储单元的写入操作之后导致阈值电压的过多或不足。此外，由于可以同时检测每页的验证结果，因此可以显着地减少时间。

6. 发明授权

US6058044A Shielded bit line sensing scheme for nonvolatile semiconductor memory 失效
标题翻译：用于非易失性半导体存储器的屏蔽位线感测方案
公开(公告)号：US6058044A
公开(公告)日：2000-05-02
申请号：US207929
申请日：1998-12-09
申请人： Yoshihisa Sugiura , Yoshihisa Iwata , Hiroshi Watanabe
发明人： Yoshihisa Sugiura , Yoshihisa Iwata , Hiroshi Watanabe
IPC分类号： G11C16/02 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C16/0483
摘要： A memory incorporates a shield bit line reading system for fixing one of two bit lines disposed adjacent to each other to a shield potential and reading data to the other bit line. Selected bit lines are precharged to a power source potential, and then brought to a floating state. The shield bit lines are fixed to the power source potential. A period in which the power source potential is applied to the selected bit lines and a period in which the power source potential is applied to the shield bit lines are the same. A source line decoder applies the power source potential to sources of NAND cell units connected to selected bit lines and applies a ground potential to sources of NAND cell units connected to shield bit lines. Then, an output of data is produced from the memory cell to the selected bit lines.
摘要翻译：存储器包括屏蔽位线读取系统，用于将彼此相邻设置的两个位线之一固定为屏蔽电位，并将数据读取到另一位线。所选位线被预充电到电源电位，然后进入浮置状态。屏蔽位线固定在电源电位上。将电源电位施加到所选位线的周期和电源电位施加到屏蔽位线的周期相同。源极线解码器将电源电位施加到连接到所选位线的NAND单元单元的源极，并将接地电位施加到与屏蔽位线连接的NAND单元单元的源极。然后，从存储器单元产生数据的输出到选择的位线。

7. 发明授权

US5327395A Page-mode type memory writing control circuit using end-of-page address 失效
标题翻译：页面模式型存储器写入控制电路使用页面地址
公开(公告)号：US5327395A
公开(公告)日：1994-07-05
申请号：US957000
申请日：1992-10-06
申请人： Yoshihisa Sugiura , Yoshihisa Iwata , Masaki Momodomi , Yasuo Itoh , Tomoharu Tanaka , Yoshiyuki Tanaka
发明人： Yoshihisa Sugiura , Yoshihisa Iwata , Masaki Momodomi , Yasuo Itoh , Tomoharu Tanaka , Yoshiyuki Tanaka
IPC分类号： G11C17/00 , G11C16/02 , G11C16/08 , G11C16/10 , G11C8/00
CPC分类号： G11C16/08 , G11C16/10 , G11C2216/14
摘要： A NOR operation is performed on the address bit by bit by a NOR circuit, and when the final address in a page is detected from the result of the NOR operation by a final address detection circuit, a program starting circuit executes data writing to a memory cell. This can ensure detection of the final address in a page without using a counter circuit. It is therefore possible to simplify the structure of the final address detection circuit and reduce the circuit area occupying in a semiconductor memory device.
摘要翻译：通过NOR电路对地址逐位执行NOR运算，并且当由最终地址检测电路从NOR运算的结果检测到页面中的最终地址时，程序启动电路执行向存储器的数据写入细胞。这可以确保在不使用计数器电路的情况下检测页面中的最终地址。因此，可以简化最终地址检测电路的结构并减少半导体存储器件占用的电路面积。

8. 发明授权

US5777930A Test potential transfer circuit 失效
标题翻译：测试电位传输电路
公开(公告)号：US5777930A
公开(公告)日：1998-07-07
申请号：US881870
申请日：1997-06-24
申请人： Yoshihisa Sugiura , Yoshihisa Iwata , Keniti Imamiya
发明人： Yoshihisa Sugiura , Yoshihisa Iwata , Keniti Imamiya
IPC分类号： G01R31/28 , G11C11/40 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/12 , G11C29/14 , G11C29/46 , H01L21/66 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/46
摘要： A potential transfer circuit consists of a first pad, a second pad, a voltage detection circuit, a level shift circuit and a switching MOS transistor. The voltage detection circuit is connected to the first pad and detects a high voltage applied to the first pad and generates a control signal which is supplied to the level shift circuit. The level shift circuit receives the control signal and generates a drive signal which is in turn supplied to the gate of the MOS transistor, causing the MOS transistor to supply to a circuit under test a test signal supplied through the second pad to the drain of the MOS transistor. In preferred embodiments, the power supply of the level shift circuit is derived from the high voltage signal supplied to the first pad.
摘要翻译：电位传输电路由第一焊盘，第二焊盘，电压检测电路，电平移位电路和开关MOS晶体管组成。电压检测电路连接到第一焊盘，并检测施加到第一焊盘的高电压，并产生提供给电平移位电路的控制信号。电平移位电路接收控制信号并产生驱动信号，该驱动信号又被提供给MOS晶体管的栅极，使MOS晶体管向被测电路提供通过第二焊盘提供的测试信号到 MOS晶体管。在优选实施例中，电平移位电路的电源由提供给第一焊盘的高电压信号导出。

9. 外观设计

USD731299S1 Clamp of a stand for supporting an object 有权
标题翻译：夹持支撑物体的支架
公开(公告)号：USD731299S1
公开(公告)日：2015-06-09
申请号：US29427205
申请日：2012-07-16
申请人： Yoshihisa Sugiura
设计人： Yoshihisa Sugiura

10. 发明授权

US07636255B2 Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07636255B2
公开(公告)日：2009-12-22
申请号：US11854048
申请日：2007-09-12
申请人： Yoshihisa Sugiura , Takashi Suzuki
发明人： Yoshihisa Sugiura , Takashi Suzuki
IPC分类号： G11C16/00
CPC分类号： G11C16/349 , G11C16/0483 , G11C27/005
摘要： A non-volatile semiconductor memory is disclosed, which comprises a plurality of memory cell arrays each having a number-of-rewrites storage region allocated to a portion of a corresponding cell array, and a number-of-rewrites write control circuit which stores the number of rewrites in cell transistors of the number-of-rewrites storage regions in non-selected memory cell arrays of the plurality of memory cell arrays by executing write of data to the cell transistors at a voltage lower than an ordinary write voltage so as to change a threshold value of the cell transistors in analog fashion according to an amount of electrons injected into floating gates of the cell transistors.
摘要翻译：公开了一种非易失性半导体存储器，其包括多个存储单元阵列，每个存储单元阵列具有分配给相应单元阵列的一部分的重写数量的存储区域，以及存储重写数量的写入控制电路通过以比普通写入电压低的电压执行数据写入到单元晶体管，在多个存储单元阵列的未选择的存储单元阵列中重写存储区域数量的单元晶体管中的重写次数，以便根据注入到单元晶体管的浮置栅极的电子量，以模拟方式改变单元晶体管的阈值。

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