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21. 发明授权

US08154051B2 MOS transistor with in-channel and laterally positioned stressors 有权
标题翻译： MOS晶体管具有通道内和侧向定位的应力源
公开(公告)号：US08154051B2
公开(公告)日：2012-04-10
申请号：US11511622
申请日：2006-08-29
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636
摘要： A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced transistor performance.
摘要翻译：可以通过将位于通道区域中的应力器与位于通道区域的相对侧上的应力源组合来提供应变通道晶体管。这在沟道区域中产生增加的应变，从而相应地增强了晶体管的性能。

22. 发明申请

US20090090935A1 High Performance CMOS Device Design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US20090090935A1
公开(公告)日：2009-04-09
申请号：US12330961
申请日：2008-12-09
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

23. 发明申请

US20060172480A1 Single metal gate CMOS device design 审中-公开
标题翻译：单金属栅CMOS器件设计
公开(公告)号：US20060172480A1
公开(公告)日：2006-08-03
申请号：US11048877
申请日：2005-02-03
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/8234
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a PMOS transistor formed on a substrate structure. The PMOS transistor includes a source and a drain each including a diffusion region in the substrate structure, a channel region defined between the source and the drain, a gate dielectric over the channel region, and a gate electrode over the gate dielectric. The gate electrode is formed of a material having an n-type work function with respect to the semiconductor substrate and is treated such that a work function of the gate electrode is converted into a mid-gap type or p-type work function with respect to the semiconductor substrate.
摘要翻译：半导体器件包括形成在衬底结构上的PMOS晶体管。 PMOS晶体管包括源极和漏极，每个源极和漏极在衬底结构中包括扩散区域，限定在源极和漏极之间的沟道区域，沟道区域上的栅极电介质，以及栅极电介质上的栅极电极。栅极由相对于半导体衬底具有n型功函数的材料形成，并且被处理为使得栅极的功函数转换为相对于第二栅极的中间间隙型或p型功函数半导体衬底。

24. 发明申请

US20060131675A1 Semiconductor device and method for high-K gate dielectrics 有权
标题翻译：用于高K栅极电介质的半导体器件和方法
公开(公告)号：US20060131675A1
公开(公告)日：2006-06-22
申请号：US11020377
申请日：2004-12-22
申请人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
发明人： Chih-Hao Wang , Ching-Wei Tsai , Shang-Chih Chen
IPC分类号： H01L29/94
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L29/1054 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor device and process including a high-k gate dielectric is described. A substrate is provided, and a high-k gate dielectric material, preferably amorphous HfSiON, is deposited over the substrate. In preferred embodiments, the high-k dielectric material includes nitrogen. In a preferred embodiment, a silicon nitride layer is deposited using jet vapor deposition (JVD) on the high-k dielectric material. When the JVD nitride layer is deposited according to preferred embodiments, the layer has a low density of charge traps, it maintains comparable carrier mobility and provides better EOT compared to oxide or oxynitride. A second nitrogen-containing layer formed between the high-k dielectric and the gate electrode acts as a diffusion barrier. It also reduces problems relating to oxygen vacancy formation in high-k dielectric and therefore minimizes Fermi-level pinning.
摘要翻译：描述了包括高k栅极电介质的半导体器件和工艺。提供衬底，并且在衬底上沉积高k栅介质材料，优选无定形HfSiON。在优选实施例中，高k电介质材料包括氮。在优选实施例中，使用喷射气相沉积（JVD）在高k电介质材料上沉积氮化硅层。当根据优选实施方案沉积JVD氮化物层时，该层具有低密度的电荷陷阱，与氧化物或氧氮化物相比，其维持可比较的载流子迁移率并提供更好的EOT。形成在高k电介质和栅电极之间的第二含氮层用作扩散阻挡层。它还减少了在高k电介质中与氧空位形成有关的问题，从而使费米能级钉扎最小化。

25. 发明申请

US20060017112A1 Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof 有权
标题翻译：具有高k栅极电介质和准金属栅极的半导体器件及其形成方法
公开(公告)号：US20060017112A1
公开(公告)日：2006-01-26
申请号：US11185443
申请日：2005-07-20
申请人： Chih-Hao Wang , Ching-Wei Tsai , Chenming Hu
发明人： Chih-Hao Wang , Ching-Wei Tsai , Chenming Hu
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L21/28123 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A process and apparatus for a semiconductor device is provided. A device comprises a first transistor having a first charge carrier type. The first transistor comprises a high-k gate dielectric and a first doped electrode. The first charge carrier type comprises one of p-type and n-type and the first doped electrode comprises the other of p-type and n-type. The device further comprises a second transistor having a charge carrier type opposite the first charge carrier type. The second transistor comprises the high-k gate dielectric, and a second doped electrode, wherein the second doped electrode comprises the other of p-type and n-type.
摘要翻译：提供了一种用于半导体器件的工艺和装置。一种器件包括具有第一电荷载流子型的第一晶体管。第一晶体管包括高k栅极电介质和第一掺杂电极。第一电荷载体类型包括p型和n型中的一种，并且第一掺杂电极包括p型和n型中的另一种。该器件还包括具有与第一电荷载体类型相反的电荷载体类型的第二晶体管。第二晶体管包括高k栅极电介质和第二掺杂电极，其中第二掺杂电极包括p型和n型中的另一种。

26. 发明授权

US07768072B2 Silicided metal gate for multi-threshold voltage configuration 有权
标题翻译：硅化金属栅极，用于多阈值电压配置
公开(公告)号：US07768072B2
公开(公告)日：2010-08-03
申请号：US11728809
申请日：2007-03-27
申请人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
发明人： Ching-Wei Tsai , Chih-Hao Wang , Wei-Jung Lin , Huan-Tsung Huang , Carlos H. Diaz
IPC分类号： H01L29/94
CPC分类号： H01L27/088 , H01L21/28097 , H01L21/82345 , H01L29/4975 , H01L29/66545 , H01L29/7833
摘要： A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not.
摘要翻译：具有改进的功函数和良好的DIBL（漏极诱发的势垒降低）和SCE（短沟道效应）特性的低电压阈值MOSFET（MOS场效应晶体管）的PMOS（p沟道金属氧化物半导体）器件，以及一种方法用于制造这样的装置。 PMOS器件包括设置在衬底上并包括硅化栅电极的栅极结构。硅化物优选为富镍，并且包括在栅电极和将栅电极与衬底分离的电介质层之间的界面处或附近的峰值铂浓度。通过多步快速热退火或类似方法制备铂峰区域。 PMOS器件还可以包括两个这样的MOSFET，其中一个是硼掺杂的，其中一个不是。

27. 发明授权

US07465972B2 High performance CMOS device design 有权
标题翻译：高性能CMOS器件设计
公开(公告)号：US07465972B2
公开(公告)日：2008-12-16
申请号：US11115484
申请日：2005-04-27
申请人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
发明人： Chih-Hao Wang , Shang-Chih Chen , Ching-Wei Tsai , Ta-Wei Wang , Pang-Yen Tsai
IPC分类号： H01L31/62
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/66553 , H01L29/66636
摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.
摘要翻译：半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。缓冲层优选具有比下面的半导体衬底更大的晶格常数。半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

28. 发明申请

US20080054301A1 MOS transistor with in-channel and laterally positioned stressors 有权
标题翻译： MOS晶体管具有通道内和侧向定位的应力源
公开(公告)号：US20080054301A1
公开(公告)日：2008-03-06
申请号：US11511622
申请日：2006-08-29
申请人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
发明人： Chih-Hao Wang , Ching-Wei Tsai , Ta-Wei Wang
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636
摘要： A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced transistor performance.
摘要翻译：可以通过将位于通道区域中的应力器与位于通道区域的相对侧上的应力源组合来提供应变通道晶体管。这在沟道区域中产生增加的应变，从而相应地增强了晶体管的性能。

29. 发明授权

US07106088B2 Method of predicting high-k semiconductor device lifetime 有权
标题翻译：预测高k半导体器件寿命的方法
公开(公告)号：US07106088B2
公开(公告)日：2006-09-12
申请号：US11077463
申请日：2005-03-10
申请人： Ching-Wei Tsai , Chih-Hao Wang , Min-Hwa Chi
发明人： Ching-Wei Tsai , Chih-Hao Wang , Min-Hwa Chi
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/2642
摘要： A preferred embodiment of the invention provides a method for testing a MISFET to determine the effect of hot carrier injection (HCI) on integrated circuit lifetime. The method comprises applying a positive stress voltage to a gate having a high-k dielectric, while simultaneously holding a drain voltage equal to the stress voltage. Using a stress voltage that is greater than a normal operating voltage accelerates the degradation and failure of the integrated circuit. Embodiments include monitoring electrical parameters such as threshold voltage, transconductance, linear drain current, or saturation drain current. A pre-selected shift in a monitored electrical parameter indicates device failure. Embodiments include analyzing the data by plotting the logarithm of an accelerated device lifetime versus the gate stress voltage. The device lifetime under operating conditions is predicted by extrapolating the plot for a given device operating voltage.
摘要翻译：本发明的优选实施例提供了一种用于测试MISFET以确定热载流子注入（HCI）对集成电路寿命的影响的方法。该方法包括对具有高k电介质的栅极施加正应力电压，同时保持等于应力电压的漏极电压。使用大于正常工作电压的应力电压可加速集成电路的劣化和故障。实施例包括监测诸如阈值电压，跨导，线性漏极电流或饱和漏极电流之类的电参数。受监控的电气参数中的预选位移表示设备故障。实施例包括通过绘制加速器件寿命与栅极应力电压的对数来分析数据。在运行条件下的器件寿命通过外推给定器件工作电压的曲线来预测。

30. 发明申请

US20060158210A1 METHOD OF PREDICTING HIGH-K SEMICONDUCTOR DEVICE LIFETIME 有权
标题翻译：预测高K半导体器件寿命的方法
公开(公告)号：US20060158210A1
公开(公告)日：2006-07-20
申请号：US11077463
申请日：2005-03-10
申请人： Ching-Wei Tsai , Chih-Hao Wang , Min-Hwa Chi
发明人： Ching-Wei Tsai , Chih-Hao Wang , Min-Hwa Chi
IPC分类号： G01R31/26
CPC分类号： G01R31/2621 , G01R31/2642
摘要： A preferred embodiment of the invention provides a method for testing a MISFET to determine the effect of hot carrier injection (HCI) on integrated circuit lifetime. The method comprises applying a positive stress voltage to a gate having a high-k dielectric, while simultaneously holding a drain voltage equal to the stress voltage. Using a stress voltage that is greater than a normal operating voltage accelerates the degradation and failure of the integrated circuit. Embodiments include monitoring electrical parameters such as threshold voltage, transconductance, linear drain current, or saturation drain current. A pre-selected shift in a monitored electrical parameter indicates device failure. Embodiments include analyzing the data by plotting the logarithm of an accelerated device lifetime versus the gate stress voltage. The device lifetime under operating conditions is predicted by extrapolating the plot for a given device operating voltage.
摘要翻译：本发明的优选实施例提供了一种用于测试MISFET以确定热载流子注入（HCI）对集成电路寿命的影响的方法。该方法包括对具有高k电介质的栅极施加正应力电压，同时保持等于应力电压的漏极电压。使用大于正常工作电压的应力电压可加速集成电路的劣化和故障。实施例包括监测诸如阈值电压，跨导，线性漏极电流或饱和漏极电流之类的电参数。受监控的电气参数中的预选位移表示设备故障。实施例包括通过绘制加速器件寿命与栅极应力电压的对数来分析数据。在运行条件下的器件寿命通过外推给定器件工作电压的曲线来预测。

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