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21. 发明申请

US20100142255A1 METHOD TO PROGRAM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT 失效
标题翻译：编程包含碳纳米管织物元件和转向元件的存储单元的方法
公开(公告)号：US20100142255A1
公开(公告)日：2010-06-10
申请号：US12693782
申请日：2010-01-26
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： G11C11/00 , H01L21/82 , H01L21/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/285 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L51/0048 , H01L51/0595 , Y10S977/742
摘要： A method of programming a carbon nanotube memory cell is provided, wherein the memory cell comprises a first conductor, a steering element, a carbon nanotube fabric, and a second conductor, wherein the steering element and the carbon nanotube fabric are arranged electrically in series between the first conductor and the second conductor, and wherein the entire carbon nanotube memory cell is formed above a substrate, the carbon nanotube fabric having a first resistivity, the method including applying a first electrical set pulse between the first conductor and the second conductor, wherein, after application of the first electrical set pulse, the carbon nanotube fabric has a second resistivity, the second resistivity less than the first resistivity. Other aspects are also provided.
摘要翻译：提供了一种编程碳纳米管存储单元的方法，其中存储单元包括第一导体，操舵元件，碳纳米管织物和第二导体，其中所述操舵元件和所述碳纳米管织物串联地电排列在第一导体和第二导体，并且其中整个碳纳米管存储单元形成在衬底上方，所述碳纳米管织物具有第一电阻率，所述方法包括在所述第一导体和所述第二导体之间施加第一电脉冲，其中在施加第一电气设备脉冲之后，碳纳米管织物具有第二电阻率，第二电阻率小于第一电阻率。还提供其他方面。

22. 发明授权

US07667999B2 Method to program a memory cell comprising a carbon nanotube fabric and a steering element 有权
标题翻译：对包含碳纳米管织物和转向元件的存储单元进行编程的方法
公开(公告)号：US07667999B2
公开(公告)日：2010-02-23
申请号：US11692144
申请日：2007-03-27
申请人： S. Brad Herner , Roy E. Scheuerlein
发明人： S. Brad Herner , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/285 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L51/0048 , H01L51/0595 , Y10S977/742
摘要： A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels.
摘要翻译：公开了一种形成可重写非易失性存储单元的方法，所述单元包括与碳纳米管织物串联的转向元件。转向元件优选为二极管，但也可以是晶体管。当经受适当的电脉冲时，碳纳米管织物可逆地改变电阻率。可以感测碳纳米管织物的不同电阻率状态，并且可以对应于存储器单元的不同数据状态。这种存储器单元的第一存储器级别可以单片地形成在衬底上方，第一存储器级单元形成在第一存储器之上，等等，形成堆叠存储器级别的高密度单片三维存储器阵列。

23. 发明申请

US20100031995A1 PHOTOVOLTAIC MODULE COMPRISING THIN LAMINAE CONFIGURED TO MITIGATE EFFICIENCY LOSS DUE TO SHUNT FORMATION 审中-公开
标题翻译：包含薄层薄膜的光伏模块配置为降低分层形成造成的效率损失
公开(公告)号：US20100031995A1
公开(公告)日：2010-02-11
申请号：US12189159
申请日：2008-08-10
申请人： S. Brad Herner , Christopher J. Petti
发明人： S. Brad Herner , Christopher J. Petti
IPC分类号： H01L31/042 , H01L31/18
CPC分类号： H01L31/046 , H01L31/18 , H01L31/186 , H01L31/1892 , Y02E10/50 , Y02P70/521
摘要： A photovoltaic cell can be formed from a thin semiconductor lamina cleaved from a substantially crystalline wafer. Shunts may inadvertently be formed through such a lamina, compromising device performance. By physically severing the lamina into a plurality of segments, the segments of the lamina preferably electrically connected in series, loss of efficiency due to shunt formation may be substantially reduced. In some embodiments, adjacent laminae are connected in series into strings, and the strings are connected in parallel to compensate for the reduction in current caused by severing the lamina into segments.
摘要翻译：光伏电池可以由从基本上晶体的晶片切割的薄的半导体层形成。分流器可能无意中通过这样的层板形成，损害了设备性能。通过将层间物理切割成多个段，优选层叠电连接的层片段，可能显着减少由于分流形成而导致的效率损失。在一些实施例中，相邻薄片串联连接成串，并且串并联连接以补偿由层切割成片段而导致的电流减少。

24. 发明授权

US07655509B2 Silicide-silicon oxide-semiconductor antifuse device and method of making 有权
标题翻译：硅化硅 - 氧化硅半导体反熔丝装置及其制造方法
公开(公告)号：US07655509B2
公开(公告)日：2010-02-02
申请号：US11898622
申请日：2007-09-13
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L23/5252 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： An antifuse contains a first silicide layer, a grown silicon oxide antifuse layer on a first surface of the first silicide layer, and a first semiconductor layer having a first surface in contact with the antifuse layer.
摘要翻译：反熔丝包含第一硅化物层，在第一硅化物层的第一表面上生长的氧化硅反熔层，以及具有与反熔丝层接触的第一表面的第一半导体层。

25. 发明授权

US07537968B2 Junction diode with reduced reverse current 有权
标题翻译：具有降低的反向电流的结二极管
公开(公告)号：US07537968B2
公开(公告)日：2009-05-26
申请号：US11765254
申请日：2007-06-19
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/82
CPC分类号： H01L29/861 , G11C17/16 , G11C17/165 , G11C2213/33 , G11C2213/71 , G11C2213/72 , H01L21/02381 , H01L21/02532 , H01L21/02667 , H01L27/1021 , H01L29/161 , H01L29/66136
摘要： A method for annealing a diode formed of a silicon-germanium alloy that minimizes leakage current is disclosed. The method includes the steps of forming semiconductor pillars of an alloy of silicon and germanium; heating the pillars at a first temperature for at least 30 minutes, and then heating the pillars at a second temperature higher than the first temperature of the alloy for up to 120 seconds. The invention further includes a monolithic three dimensional memory array of a plurality of p-i-n diodes, the p-i-n diodes being formed of a silicon-germanium alloy that have been subjected to a two-stage heating process.
摘要翻译：公开了一种使由硅 - 锗合金形成的二极管退火的方法，其使泄漏电流最小化。该方法包括形成硅和锗的合金的半导体柱的步骤; 在第一温度下加热柱子至少30分钟，然后在高于合金的第一温度的第二温度下加热柱子长达120秒。本发明还包括多个p-i-n二极管的单片三维存储器阵列，p-i-n二极管由已进行两级加热处理的硅 - 锗合金形成。

26. 发明申请

US20080316808A1 Nonvolatile memory device containing carbon or nitrogen doped diode 失效
标题翻译：包含碳或氮掺杂二极管的非易失性存储器件
公开(公告)号：US20080316808A1
公开(公告)日：2008-12-25
申请号：US11819042
申请日：2007-06-25
申请人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
发明人： S. Brad Herner , Mark H. Clark , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C11/36
摘要： A nonvolatile memory device includes at least one nonvolatile memory cell which comprises a silicon, germanium or silicon-germanium diode which is doped with at least one of carbon or nitrogen in a concentration greater than an unavoidable impurity level concentration.
摘要翻译：非易失性存储器件包括至少一个非易失性存储单元，其包括硅，锗或硅 - 锗二极管，其掺杂有浓度大于不可避免的杂质水平浓度的碳或氮中的至少一种。

27. 发明申请

US20080239787A1 LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT 有权
标题翻译：指向具有大电流和均匀电流的上行P-I-N二极管的大阵列
公开(公告)号：US20080239787A1
公开(公告)日：2008-10-02
申请号：US11692153
申请日：2007-03-27
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： G11C11/00 , H01L27/08
CPC分类号： H01L45/122 , B82Y10/00 , G11C13/0007 , G11C17/16 , G11C2213/16 , G11C2213/32 , G11C2213/71 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/149 , H01L45/16 , Y10S977/742 , Y10S977/842
摘要： An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.
摘要翻译：公开了由沉积的硅，锗或硅 - 锗形成的向上指向的p-i-n二极管。二极管具有底部重掺杂p型区域，中间固有或轻掺杂区域和顶部重掺杂n型区域。顶部重掺杂p型区掺杂砷，二极管的半导体材料与适当的硅化物，锗化物或硅化锗 - 锗化物接触结晶。当施加高于二极管的导通电压的电压时，可以形成具有优异的跨阵列电流均匀性的这种向上指向二极管的大阵列。该二极管有利地用于单片三维存储器阵列中。

28. 发明授权

US07276403B2 Selective oxidation of silicon in diode, TFT, and monolithic three dimensional memory arrays 失效
标题翻译：二极管，TFT和单片三维存储阵列中硅的选择性氧化
公开(公告)号：US07276403B2
公开(公告)日：2007-10-02
申请号：US11237162
申请日：2005-09-28
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/84
CPC分类号： H01L27/1021 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/12
摘要： The present invention relates to use of selective oxidation to oxidize silicon in the presence of tungsten and/or tungsten nitride in memory cells and memory arrays. This technique is especially useful in monolithic three dimensional memory arrays. In one aspect of the invention, the silicon of a diode-antifuse memory cell is selectively oxidized to repair etch damage and reduce leakage, while exposed tungsten of adjacent conductors and tungsten nitride of a barrier layer are not oxidized. In some embodiments, selective oxidation may be useful for gap fill. In another aspect of the invention, TFT arrays made up of charge storage memory cells comprising a polysilicon/tungsten nitride/tungsten gate can be subjected to selective oxidation to passivate the gate polysilicon and reduce leakage.
摘要翻译：本发明涉及选择性氧化在存在于存储器单元和存储器阵列中的钨和/或氮化钨存在下氧化硅的用途。这种技术在单片三维存储器阵列中特别有用。在本发明的一个方面，二极管 - 反熔断存储器单元的硅被选择性地氧化以修复蚀刻损伤并减少泄漏，而相邻导体的暴露的钨和阻挡层的氮化钨不被氧化。在一些实施方案中，选择性氧化可用于间隙填充。在本发明的另一方面，可以对包括多晶硅/氮化钨/钨栅极的电荷存储单元组成的TFT阵列进行选择性氧化，以钝化栅多晶硅并减少泄漏。

29. 发明授权

US07238607B2 Method to minimize formation of recess at surface planarized by chemical mechanical planarization 有权
标题翻译：通过化学机械平面化平坦化的表面减少凹陷形成的方法
公开(公告)号：US07238607B2
公开(公告)日：2007-07-03
申请号：US11237169
申请日：2005-09-28
申请人： Samuel V. Dunton , S. Brad Herner
发明人： Samuel V. Dunton , S. Brad Herner
IPC分类号： H01L21/4763
CPC分类号： G11C11/39 , G11C5/02 , G11C17/16 , G11C2213/71 , G11C2213/77
摘要： When chemical mechanical planarization (CMP) is used to planarize a surface coexposing patterned features and dielectric fill, where patterned features and the fill are formed of materials having very different CMP removal rates or characteristics, the planarized surface may have excessively rough, dishing or recessing may take place, or one or more or the materials may be damaged. In structures in which planarity is important, these problems can be prevented by forming a capping layer on the patterned features, wherein the CMP removal rate of the material forming the capping layer is similar to the CMP removal rate of the dielectric fill.
摘要翻译：当化学机械平面化（CMP）用于平坦化表面共同图案化特征和电介质填充时，其中图案特征和填充物由具有非常不同的CMP去除速率或特性的材料形成，平坦化表面可能具有过度粗糙，凹陷或凹陷可能发生，或者一个或多个，或者材料可能被损坏。在平面度重要的结构中，通过在图案化特征上形成覆盖层可以防止这些问题，其中形成覆盖层的材料的CMP去除速率类似于介电填料的CMP去除速率。

30. 发明授权

US06956278B2 Low-density, high-resistivity titanium nitride layer for use as a contact for low-leakage dielectric layers 有权
标题翻译：低密度，高电阻率氮化钛层，用作低漏电介质层的接触
公开(公告)号：US06956278B2
公开(公告)日：2005-10-18
申请号：US10611245
申请日：2003-06-30
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/02 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L23/525 , H01L29/49 , H01L29/78 , H01L29/00 , H01L29/04
CPC分类号： H01L23/5252 , H01L21/28088 , H01L21/28273 , H01L21/28282 , H01L21/2855 , H01L21/3205 , H01L28/60 , H01L29/4966 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A low-density, high-resistivity layer of a PVD sputter-deposited material, preferably titanium nitride, when coupled with a dielectric, makes a superior low-leakage insulating barrier for use in semiconductor devices. The material is created by sputtering methods that cause the ions to strike the deposition surface with reduced energy, for example in an ion metal plasma chamber with no self-bias accelerating ions normal to the deposition surface, or in a standard PVD chamber with pressure increased.
摘要翻译：当与电介质耦合时，PVD溅射沉积材料（优选氮化钛）的低密度，高电阻率层产生用于半导体器件的优异的低漏电绝缘屏障。该材料是通过溅射方法产生的，这些方法使离子以较低的能量冲击沉积表面，例如在离子金属等离子体室中，没有自偏压加速垂直于沉积表面的离子，或者在具有压力增加的标准PVD室中。

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