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    • 23. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME
    • 非易失性半导体存储器件及其制造方法
    • US20080246072A1
    • 2008-10-09
    • US11773721
    • 2007-07-05
    • Masaki KondoTakashi IzumidaNobutoshi AokiToshiharu Watanabe
    • Masaki KondoTakashi IzumidaNobutoshi AokiToshiharu Watanabe
    • H01L29/788
    • H01L27/115H01L27/11521H01L27/11524
    • In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor.
    • 在包括存储单元列的非易失性半导体存储器件中,该存储单元列是通过串联连接多个存储单元而形成的,每个存储单元具有通过绝缘层在半导体衬底上层叠电荷存储层和控制栅极的结构,第一选择 形成在半导体衬底上并连接在存储单元列的一端和公共源极线之间的晶体管,以及形成在半导体衬底上并连接在存储单元列的另一端和位线之间的第二选择晶体管, 部分形成在第一选择晶体管和与第一选择晶体管相邻的存储单元之间的半导体衬底的表面上,并且凹陷部分中的第一选择晶体管的一侧的边缘到达第二选择晶体管的一侧的端部 第一选择晶体管的栅极中的存储单元。
    • 30. 发明授权
    • Method of manufacturing semiconductor devices with alleviated electric field concentration at gate edge portions
    • 制造半导体器件的方法,该栅极边缘部分具有减小的电场浓度
    • US06228717B1
    • 2001-05-08
    • US09196002
    • 1998-11-19
    • Hiroaki HazamaKazumi AmemiyaToshiharu Watanabe
    • Hiroaki HazamaKazumi AmemiyaToshiharu Watanabe
    • H01K218247
    • H01L29/42368H01L21/28247H01L21/28273H01L29/42324H01L29/511
    • With the present invention, in a memory cell of a stacked-gate NOR flash EEPROM, for example, a SiON film is selectively formed on the sidewalls of a floating gate electrode and the top surface and sidewalls of a control gate electrode. Thereafter, annealing is done in an oxidative atmosphere, thereby carrying out a post-oxidation process. This allows an oxide film to grow gradually at the gate edge portions contacting a tunnel oxide film or interlayer insulating film of the floating gate electrode and control gate electrode. The formation of the SiON film on at least on the sidewalls of the floating gate electrode prevents oxidation at those portions. On the other hand, the gate edge portions of the floating gate electrode eventually become round. By improving the shape of the gate edge portions of the floating gate electrode in this way, an electric field is prevented from concentrating at the gate edge portions of the floating gate electrode.
    • 通过本发明,在堆叠栅极NOR闪存EEPROM的存储单元中,例如,在浮栅电极的侧壁和控制栅电极的顶表面和侧壁上选择性地形成SiON膜。 此后,在氧化气氛中进行退火,从而进行后氧化工序。 这允许氧化膜在与浮栅电极和控制栅电极的隧道氧化物膜或层间绝缘膜接触的栅极边缘部分处逐渐生长。 至少在浮栅电极的侧壁上形成SiON膜可防止这些部分的氧化。 另一方面,浮栅电极的栅极边缘部分最终变圆。 通过以这种方式改善浮栅电极的栅边缘部分的形状,防止了电场集中在浮栅电极的栅极边缘部分。