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21. 发明申请

US20070099417A1 Adhesion and minimizing oxidation on electroless CO alloy films for integration with low K inter-metal dielectric and etch stop 审中-公开
标题翻译：粘附和最小化无电解CO合金膜上的氧化，用于与低K金属间电介质和蚀刻停止集成
公开(公告)号：US20070099417A1
公开(公告)日：2007-05-03
申请号：US11329785
申请日：2006-01-10
申请人： Hongbin Fang , Timothy Weidman , Fang Mei , Yaxin Wang , Arulkumar Shanmugasundram , Christopher Bencher , Mehul Naik
发明人： Hongbin Fang , Timothy Weidman , Fang Mei , Yaxin Wang , Arulkumar Shanmugasundram , Christopher Bencher , Mehul Naik
IPC分类号： H01L21/469
CPC分类号： H01L21/76843 , H01L21/76829 , H01L21/76846 , H01L21/76849 , H01L21/76862 , H01L21/76864
摘要： A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on the substrate, reducing oxide formation on the capping layer, and then depositing a dielectric material. A method and apparatus for processing a semiconductor substrate including depositing a capping layer upon a conductive material formed on a substrate, exposing the capping layer to a plasma, heating the substrate to more than about 100° C., and depositing a low dielectric constant material.
摘要翻译：一种用于处理半导体衬底的方法和装置，包括在形成在衬底上的导电材料上沉积覆盖层，减少覆盖层上的氧化物形成，然后沉积电介质材料。一种用于处理半导体衬底的方法和装置，包括在形成在衬底上的导电材料上沉积覆盖层，将覆盖层暴露于等离子体，将衬底加热到大于约100℃，以及沉积低介电常数材料。

22. 发明授权

US07034409B2 Method of eliminating photoresist poisoning in damascene applications 失效
公开(公告)号：US07034409B2
公开(公告)日：2006-04-25
申请号：US10718887
申请日：2003-11-21
申请人： Ping Xu , Li-Qun Xia , Larry A. Dworkin , Mehul Naik
发明人： Ping Xu , Li-Qun Xia , Larry A. Dworkin , Mehul Naik
IPC分类号： H01L29/12
CPC分类号： H01L21/0234 , C23C16/325 , C23C16/401 , G03F7/16 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02271 , H01L21/3105 , H01L21/31144 , H01L21/312 , H01L21/3148 , H01L21/7681 , H01L21/76826 , H01L21/76828 , H01L21/76832 , Y10S257/914
摘要： A method is provided for processing a substrate including treating a surface of a dielectric layer comprising silicon and carbon by exposing the dielectric layer comprising silicon and carbon to a plasma of an inert gas, and depositing a photoresist on the dielectric layer comprising silicon and carbon. The dielectric layer may comprise a first dielectric layer comprising silicon, carbon, and nitrogen, and a second layer of nitrogen-free silicon and carbon containing material in situ on the first dielectric layer, and a third dielectric layer comprising silicon, oxygen, and carbon on the second dielectric layer.

23. 发明申请

US20050158667A1 Solvent free photoresist strip and residue removal processing for post etching of low-k films 审中-公开
标题翻译：无溶剂的光致抗蚀剂条和残留物去除处理用于低k膜的后蚀刻
公开(公告)号：US20050158667A1
公开(公告)日：2005-07-21
申请号：US10761122
申请日：2004-01-20
申请人： Huong Thanh Nguyen , Mark Naoshi Kawaguchi , Mehul Naik , Li-Qun Xia , Ellie Yieh
发明人： Huong Thanh Nguyen , Mark Naoshi Kawaguchi , Mehul Naik , Li-Qun Xia , Ellie Yieh
IPC分类号： G03F7/00 , G03F7/36 , G03F7/42 , H01L21/02 , H01L21/311
CPC分类号： G03F7/427 , H01L21/02063 , H01L21/31138
摘要： A photoresist or a residue of the photoresist may by removed by the hydrogen and water plasma mixture. The process may be performed at a temperature range between about 150° C. and about 450° C., preferably about 250° C., and a power range between about 500 W and about 3000 W, preferably about 1400 W.
摘要翻译：可以通过氢和水等离子体混合物去除光致抗蚀剂或光致抗蚀剂的残余物。该方法可以在约150℃至约450℃，优选约250℃的温度范围和约500W至约3000W，优选约1400W的功率范围内进行。

24. 发明授权

US06548396B2 Method of producing an interconnect structure for an integrated circuit 失效
公开(公告)号：US06548396B2
公开(公告)日：2003-04-15
申请号：US09874874
申请日：2001-06-05
申请人： Mehul Naik , Samuel Broydo
发明人： Mehul Naik , Samuel Broydo
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

25. 发明授权

US08563095B2 Silicon nitride passivation layer for covering high aspect ratio features 有权
标题翻译：用于覆盖高纵横比特征的氮化硅钝化层
公开(公告)号：US08563095B2
公开(公告)日：2013-10-22
申请号：US12724396
申请日：2010-03-15
申请人： Nagarajan Rajagopalan , Xinhai Han , Ryan Yamase , Ji Ae Park , Shamik Patel , Thomas Nowak , Zhengjiang “David” Cui , Mehul Naik , Heung Lak Park , Ran Ding , Bok Hoen Kim
发明人： Nagarajan Rajagopalan , Xinhai Han , Ryan Yamase , Ji Ae Park , Shamik Patel , Thomas Nowak , Zhengjiang “David” Cui , Mehul Naik , Heung Lak Park , Ran Ding , Bok Hoen Kim
IPC分类号： H05H1/24 , C23C16/34
CPC分类号： H01L21/02068 , C23C16/345 , C23C16/45523 , H01L21/0217 , H01L21/02271 , H01L21/02274 , H01L21/0234 , H01L21/56 , H01L21/76832 , H01L21/76834 , H01L23/291 , H01L23/3171 , H01L24/11 , H01L24/13 , H01L24/742 , H01L2224/1181 , H01L2224/1182 , H01L2224/11827 , H01L2224/11831 , H01L2224/119 , H01L2224/11901 , H01L2224/13025 , H01L2224/131 , H01L2224/13147 , H01L2224/13562 , H01L2224/1358 , H01L2224/13583 , H01L2224/13687 , H01L2224/742 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/05042 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.
摘要翻译：描述了在衬底的特征上形成包括氮化硅的钝化层的方法。在沉积方法的第一阶段中，将包含含硅气体和含氮气体的介电沉积气体引入工艺区域并通电以沉积氮化硅层。在第二阶段中，将具有不同于介电沉积气体的组成不同的处理气体引入处理区并通电以处理氮化硅层。第一和第二阶段可以执行多次。

26. 发明授权

US08329575B2 Fabrication of through-silicon vias on silicon wafers 有权
标题翻译：在硅晶片上制造通硅通孔
公开(公告)号：US08329575B2
公开(公告)日：2012-12-11
申请号：US12977060
申请日：2010-12-22
申请人： Nagarajan Rajagopalan , Ji Ae Park , Ryan Yamase , Shamik Patel , Thomas Nowak , Li-Qun Xia , Bok Hoen Kim , Ran Ding , Jim Baldino , Mehul Naik , Sesh Ramaswami
发明人： Nagarajan Rajagopalan , Ji Ae Park , Ryan Yamase , Shamik Patel , Thomas Nowak , Li-Qun Xia , Bok Hoen Kim , Ran Ding , Jim Baldino , Mehul Naik , Sesh Ramaswami
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/31
CPC分类号： H01L24/13 , H01L21/02074 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/3065 , H01L21/31116 , H01L21/67103 , H01L21/67109 , H01L21/6719 , H01L21/6835 , H01L21/68792 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76898 , H01L24/11 , H01L24/742 , H01L2221/68372 , H01L2221/68381 , H01L2224/11002 , H01L2224/11452 , H01L2224/1182 , H01L2224/13562 , H01L2224/1357 , H01L2224/13687 , H01L2224/742 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01068 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/351 , H01L2924/05042 , H01L2924/00
摘要： A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.
摘要翻译：一种硅通孔制造方法包括蚀刻硅板中的多个通孔。在硅板的表面和通孔的侧壁和底壁上沉积氧化物衬垫。然后将金属导体沉积在通孔中。在可与氧化物衬垫同时使用的另一种方案中，氮化硅钝化层沉积在衬底的硅板的暴露后表面上。

27. 发明申请

US20110104891A1 METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY 审中-公开
标题翻译：用于减少RC延迟的电介质层中产生气泡的方法和装置
公开(公告)号：US20110104891A1
公开(公告)日：2011-05-05
申请号：US12986809
申请日：2011-01-07
申请人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang David Cui , Mihaela Balseanu , Meiyee Maggie Le Shek , Li-Qun Xia
发明人： AMIR AL-BAYATI , Alexandros T. Demos , Kang Sub Yim , Mehul Naik , Zhenjiang David Cui , Mihaela Balseanu , Meiyee Maggie Le Shek , Li-Qun Xia
IPC分类号： H01L21/768
CPC分类号： H01L21/7682 , H01L21/3105 , H01L21/31111 , H01L21/31144 , H01L21/76825 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.
摘要翻译：一种用于在互连结构的电介质材料中产生气隙的方法和装置。一个实施例提供了一种用于形成半导体结构的方法，包括在衬底上沉积第一介电层，在第一介电层中形成沟槽，用导电材料填充沟槽，平坦化导电材料以暴露第一介电层，在导电材料和暴露的第一电介质层上的阻挡膜，在介电阻挡膜上沉积硬掩模层，在介电阻挡膜和硬掩模层中形成图案，以暴露衬底的选定区域，氧化至少一部分在衬底的选定区域中的第一介电层，去除第一电介质层的氧化部分以在导电材料周围形成反向沟槽，以及在反向沟槽中形成气隙，同时在反向沟槽中沉积第二电介质材料。

28. 发明授权

US07811924B2 Air gap formation and integration using a patterning cap 有权
标题翻译：使用图案化盖的气隙形成和一体化
公开(公告)号：US07811924B2
公开(公告)日：2010-10-12
申请号：US12336884
申请日：2008-12-17
申请人： Zhenjiang Cui , Mehul Naik , Christopher D. Bencher , Kenneth MacWilliams
发明人： Zhenjiang Cui , Mehul Naik , Christopher D. Bencher , Kenneth MacWilliams
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/02115 , H01L21/02271 , H01L21/0337 , H01L21/31144 , H01L21/3146 , H01L21/7682 , H01L21/76831 , H01L21/76832 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Methods for patterning films and their resulting structures. In an embodiment, an amorphous carbon mask is formed over a substrate, such as a damascene layer. A spacer layer is deposited over the amorphous carbon mask and the spacer layer is etched to form a spacer and to expose the amorphous carbon mask. The amorphous carbon mask is removed selectively to the spacer to expose the substrate layer. A gap fill layer is deposited around the spacer to cover the substrate layer but expose the spacer. The spacer is removed selectively to form a gap fill mask over the substrate. The pattern of the gap fill mask is transferred, in one implementation, into a damascene layer to remove at least a portion of an IMD and form an air gap.
摘要翻译：膜图案及其结果的方法。在一个实施方案中，在诸如镶嵌层的基底上形成无定形碳掩模。在无定形碳掩模上沉积间隔层，并且蚀刻间隔层以形成间隔物并暴露无定形碳掩模。无定形碳掩模被选择性地去除到间隔物以暴露衬底层。间隔填充层沉积在间隔物周围以覆盖基底层，但暴露间隔物。选择性地移除间隔物以在衬底上形成间隙填充掩模。间隙填充掩模的图案在一个实施方式中转移到镶嵌层中以去除IMD的至少一部分并形成气隙。

29. 发明申请

US20090317628A1 METHODS AND APPARTUS TO PREVENT CONTAMINATION OF A PHOTORESIST LAYER ON A SUBSTRATE 审中-公开
标题翻译：防止基片上的光电陶瓷层污染的方法和装置
公开(公告)号：US20090317628A1
公开(公告)日：2009-12-24
申请号：US12176392
申请日：2008-07-20
申请人： Mehul Naik , Keisuke Mizuuchi , Huixiong Dai , Michael Armacost , Li-Qun Xia
发明人： Mehul Naik , Keisuke Mizuuchi , Huixiong Dai , Michael Armacost , Li-Qun Xia
IPC分类号： B32B9/00
CPC分类号： H01L21/31144 , H01L21/3105 , H01L21/76829 , Y10T428/261
摘要： In one aspect, a method is provided which includes (1) providing a substrate including a photoresist layer and an additional layer which may be a potential source of contaminants, and (2) preventing a release of contaminants from the additional layer, wherein preventing the release of contaminants from the additional layer protects the photoresist layer from exposure to contaminants from the additional layer. Numerous other aspects are provided.
摘要翻译：在一个方面，提供了一种方法，其包括（1）提供包括光致抗蚀剂层的基材和可能是潜在的污染源的附加层，和（2）防止污染物从附加层释放，其中防止污染物从附加层的释放保护光致抗蚀剂层免受来自附加层的污染物的侵害。提供了许多其他方面。

30. 发明申请

US20080124924A1 Scheme for copper filling in vias and trenches 审中-公开
标题翻译：通孔和沟槽中铜填充方案
公开(公告)号：US20080124924A1
公开(公告)日：2008-05-29
申请号：US11488514
申请日：2006-07-18
申请人： Mehul Naik
发明人： Mehul Naik
IPC分类号： H01L21/768
CPC分类号： H01L21/28556 , C23C18/08 , H01L21/76843 , H01L21/76871
摘要： Embodiments of the present invention generally relate to methods and apparatuses using supercritical fluids and/or dense fluids to deposit a metal material on the surface of a substrate. In one embodiment, a metal material layer is deposited by applying a supercritical fluid, a dense fluid, or combinations thereof and a metal-containing precursor to the surface of a substrate inside a substrate processing chamber. In another embodiment, a first metal material and a second metal material is sequentially deposited and annealing is performed to form a metal alloy material on the surface of a substrate. In still another embodiment, a copper material layer is deposited by applying a supercritical fluid, a dense fluid, or combinations thereof and a copper containing precursor to the surface of the substrate.
摘要翻译：本发明的实施方案一般涉及使用超临界流体和/或致密流体将金属材料沉积在基底表面上的方法和装置。在一个实施例中，通过将超临界流体，致密流体或其组合和含金属的前体施加到衬底处理室内的衬底的表面来沉积金属材料层。在另一个实施例中，顺序地沉积第一金属材料和第二金属材料，并执行退火以在基板的表面上形成金属合金材料。在另一个实施例中，通过将超临界流体，致密流体或其组合和含铜前体施加到基底的表面来沉积铜材料层。

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