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21. 发明申请

US20110220862A1 RESISTANCE VARIABLE ELEMENT AND RESISTANCE VARIABLE MEMORY DEVICE 有权
标题翻译：电阻可变元件和电阻可变存储器件
公开(公告)号：US20110220862A1
公开(公告)日：2011-09-15
申请号：US13128575
申请日：2010-07-12
申请人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
发明人： Koji Arita , Takumi Mikawa , Atsushi Himeno , Yoshio Kawashima , Kenji Tominaga
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1666 , H01L45/1675
摘要： A resistance variable element (100) used in a through-hole cross-point structure memory device, according to the present invention, and a resistance variable memory device including the resistance variable element, includes a substrate (7) and an interlayer insulating layer (3) formed on the substrate, and have a configuration in which a through-hole (4) is formed to penetrate the interlayer insulating layer, a first resistance variable layer (2) comprising transition metal oxide is formed outside the through-hole, a second resistance variable layer (5) comprising transition metal oxide is formed inside the through-hole, the first resistance variable layer is different in resistivity from the second resistance variable layer, and the first resistance variable layer and the second resistance variable layer are in contact with each other only in an opening (20) of the through-hole which is closer to the substrate.
摘要翻译：在根据本发明的通孔交叉点结构存储装置中使用的电阻可变元件（100）和包括电阻可变元件的电阻变化存储装置包括基板（7）和层间绝缘层（ 3），并且具有形成贯通层间绝缘层的通孔（4）的构造，在通孔的外侧形成有包含过渡金属氧化物的第一电阻变化层（2），在通孔内形成有包含过渡金属氧化物的第二电阻变化层（5），第一电阻变化层的电阻率与第二电阻变化层不同，第一电阻变化层和第二电阻变化层接触彼此仅在更靠近基板的通孔的开口（20）中。

22. 发明申请

US20110220861A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110220861A1
公开(公告)日：2011-09-15
申请号：US13126975
申请日：2009-07-16
申请人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
发明人： Atsushi Himeno , Takumi Mikawa , Yoshio Kawashima
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1683
摘要： A nonvolatile semiconductor memory device which can achieve miniaturization and a larger capacity in a cross-point structure in which memory cells are formed inside contact holes at cross points of word lines and bit lines, respectively, and a manufacturing method thereof are provided. A nonvolatile semiconductor memory device comprises a substrate; a plurality of stripe-shaped lower copper wires (70) formed on the substrate; an interlayer insulating layer (76) formed on the substrate provided with the lower copper wires (70), a plurality of contact holes penetrating interlayer insulating layer (76) to surfaces of the lower copper wires (70), respectively; electrode seed layers (77) and precious metal electrode layers (78) formed only at bottoms of the contact holes, respectively; resistance variable layers (73) filled into the contact holes such that the resistance variable layers are connected to the precious metal electrode layers (73), respectively; a plurality of stripe-shaped upper copper wires (74) connected to the resistance variable layers (73), respectively, and cross the lower copper wires (70), respectively, and the electrode seed layers (77) and the precious metal electrode layers (78) are formed by selective growth plating.
摘要翻译：提供一种非易失性半导体存储器件及其制造方法，该非易失性半导体存储器件分别在字线和位线的交叉点处的接触孔内部形成存储单元的交叉点结构中的小型化和较大容量。非易失性半导体存储器件包括衬底; 形成在所述基板上的多个条状下部铜线（70）形成在设置有下铜线（70）的基板上的层间绝缘层（76），分别向下铜线（70）的表面贯穿层间绝缘层（76）的多个接触孔; 电极种子层（77）和仅在接触孔的底部形成的贵金属电极层（78）; 电阻变化层（73）填充到接触孔中，使得电阻变化层分别连接到贵金属电极层（73）; 分别连接到电阻变化层（73）的多个条状上部铜线（74），并分别与下部铜线（70）交叉，电极种子层（77）和贵金属电极层（78）通过选择性生长电镀形成。

23. 发明授权

US07557011B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07557011B2
公开(公告)日：2009-07-07
申请号：US11280250
申请日：2005-11-17
申请人： Takumi Mikawa , Yuji Judai , Toshie Kutsunai
发明人： Takumi Mikawa , Yuji Judai , Toshie Kutsunai
IPC分类号： H01L21/108 , H01L21/316 , H01L21/318
CPC分类号： H01L28/65 , H01L27/11507 , H01L28/57 , H01L28/75
摘要： A semiconductor device includes a first hydrogen barrier film, a capacitor device formed on the first hydrogen barrier film, and a second hydrogen barrier film formed to cover the capacitor device. The first and second hydrogen barrier films each contain at least one common type of atoms for allowing the first and second hydrogen barrier films to adhere to each other.
摘要翻译：半导体器件包括第一氢阻挡膜，形成在第一氢阻挡膜上的电容器器件和形成为覆盖电容器器件的第二氢阻挡膜。第一和第二氢阻挡膜每个含有至少一种常见类型的原子，用于允许第一和第二氢阻挡膜彼此粘附。

24. 发明申请

US20090014710A1 NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY APPARATUS, AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：非易失性存储元件，非易失性存储器件及其制造方法
公开(公告)号：US20090014710A1
公开(公告)日：2009-01-15
申请号：US12281034
申请日：2007-03-06
申请人： Yoshio Kawashima , Takeshi Takagi , Takumi Mikawa , Zhiqiang Wei
发明人： Yoshio Kawashima , Takeshi Takagi , Takumi Mikawa , Zhiqiang Wei
IPC分类号： H01L45/00
CPC分类号： H01L27/101 , H01L27/2409 , H01L27/2463 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1658 , H01L45/1675
摘要： A lower electrode layer 2, an upper electrode layer 4 formed above the lower electrode layer 2, and a metal oxide thin film layer 3 formed between the lower electrode layer 2 and the upper electrode layer 4 are provided. The metal oxide thin film layer 3 includes a first region 3a whose value of resistance increases or decreases by an electric pulse that is applied between the lower electrode layer 2 and the upper electrode layer 4 and a second region 3b arranged around the first region 3a and having a larger content of oxygen than the first region 3a, wherein the lower and upper electrode layers 2 and 4 and at least a part of the first region 3a are arranged so as to overlap as viewed from the direction of the thickness of the first region 3a.
摘要翻译：设置下电极层2，形成在下电极层2上的上电极层4和形成在下电极层2和上电极层4之间的金属氧化物薄膜层3。金属氧化物薄膜层3包括第一区域3a，其第一区域3a的电阻值通过施加在下电极层2和上电极层4之间的电脉冲和围绕第一区域3a布置的第二区域3b而增大或减小，以及具有比第一区域3a更大的氧含量，其中下电极层2和上电极层4以及第一区域3a的至少一部分从第一区域的厚度方向观察而重叠 3a。

25. 发明授权

US07413949B2 Capacitor and method for fabricating the same 失效
标题翻译：电容器及其制造方法
公开(公告)号：US07413949B2
公开(公告)日：2008-08-19
申请号：US11117328
申请日：2005-04-29
申请人： Takumi Mikawa , Yuji Judai , Shinichiro Hayashi
发明人： Takumi Mikawa , Yuji Judai , Shinichiro Hayashi
IPC分类号： H01L21/8242
CPC分类号： H01L28/55 , H01L28/60 , Y10T29/43
摘要： A capacitor is formed on an interlayer insulating film formed on a semiconductor substrate. The capacitor includes a bottom electrode made of platinum, a capacitor insulating film made of SrTaBiO (SBT) containing an element absorbing hydrogen such as titanium, for example, in grain boundaries, inter-lattice positions or holes, and a top electrode made of platinum.
摘要翻译：在形成在半导体衬底上的层间绝缘膜上形成电容器。电容器包括由铂制成的底部电极，由SrTaBiO（SBT）制成的电容器绝缘膜，其包含例如在晶界，晶格间位置或空穴中吸收钛的钛的元素，以及由铂制成的顶部电极。

26. 发明授权

US07115937B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07115937B2
公开(公告)日：2006-10-03
申请号：US11270156
申请日：2005-11-09
申请人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
发明人： Takumi Mikawa , Yuuji Jyuudai , Shinya Natsume
IPC分类号： H01L27/108
CPC分类号： H01L28/60 , H01L21/31053 , H01L27/11502 , H01L27/11507
摘要： A method for manufacturing a semiconductor device includes the steps of forming a conductive layer over a first insulating layer formed on a substrate, and over a plurality of contact plugs formed in the first insulating layer; forming a plurality of capacitor element lower electrodes by patterning the conductive layer; forming a second insulating layer on the first insulating layer and the capacitor element lower electrodes; forming recesses in the second insulating layer at a region above the capacitor element lower electrodes; planarizing the second insulating layer by polishing; exposing the capacitor element lower electrodes; and forming a capacitive insulating film and capacitor element upper electrodes above the capacitor element lower electrodes. In polishing the second insulating layer, leveling of steps can be accelerated, insufficient polishing, peeling of the lower electrodes and generation of scratches can be suppressed, and the global step difference can be reduced.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在形成于基板上的第一绝缘层上形成导电层，以及形成在第一绝缘层中的多个接触插塞; 通过图案化导电层形成多个电容器元件下电极; 在所述第一绝缘层和所述电容器元件下电极上形成第二绝缘层; 在所述电容器元件下电极上方的区域中在所述第二绝缘层中形成凹部; 通过抛光来平坦化第二绝缘层; 暴露电容元件下电极; 以及在电容器元件下电极之上形成电容绝缘膜和电容元件上电极。在第二绝缘层的研磨中，可以加速台阶的调平，不足的研磨，下部电极的剥离和划痕的产生也可以抑制，从而可以降低全局的步进差。

27. 发明授权

US06963095B2 Ferroelectric memory device and method for fabricating the same 有权
标题翻译：铁电存储器件及其制造方法
公开(公告)号：US06963095B2
公开(公告)日：2005-11-08
申请号：US10632931
申请日：2003-08-04
申请人： Takumi Mikawa , Toshie Kutsunai , Yuji Judai
发明人： Takumi Mikawa , Toshie Kutsunai , Yuji Judai
IPC分类号： H01L27/105 , H01L21/02 , H01L21/321 , H01L21/768 , H01L21/8246 , H01L27/115 , H01L29/72
CPC分类号： H01L28/65 , H01L21/3212 , H01L27/11502 , H01L27/11507 , H01L28/57
摘要： The ferroelectric memory device has a plurality of capacitor elements each formed on a semiconductor substrate and composed of a lower electrode, a capacitor insulating film made of a ferroelectric material formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. Each of the lower electrodes is buried in a burying insulating film to have an upper surface planarized relative to the upper surface of the burying insulating film and has a plane configuration such that the distance from an arbitrary position on the upper surface of the lower electrode to the nearest end portion thereof is 0.6 μm or less.
摘要翻译：铁电存储器件具有多个电容器元件，每个电容器元件形成在半导体衬底上，由下电极，形成在下电极上的铁电材料制成的电容器绝缘膜和形成在电容器绝缘膜上的上电极组成。每个下电极被埋在埋入绝缘膜中以使上表面相对于掩埋绝缘膜的上表面平坦化，并且具有平面构造，使得从下电极的上表面上的任意位置到下电极的距离其最接近的端部为0.6μm以下。

28. 发明授权

US06960800B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06960800B2
公开(公告)日：2005-11-01
申请号：US09734176
申请日：2000-12-12
申请人： Takumi Mikawa , Yuji Judai
发明人： Takumi Mikawa , Yuji Judai
IPC分类号： H01G4/12 , H01L21/02 , H01L21/203 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/76 , H01L23/48 , H01L23/52 , H01L29/00
CPC分类号： H01L28/55 , H01L28/60 , H01L28/75
摘要： A lower electrode is formed on a substrate, a capacitive insulating film is formed out of a ferroelectric film on the lower electrode, and an upper electrode is formed on the capacitive insulating film. A contact layer is formed on the upper electrode. The contact layer is either a single-layer film made of a metal oxide or a metal nitride or a multilayer structure made up of metal oxide and metal nitride films. An insulating film is formed to cover the lower electrode, capacitive insulating film, upper electrode and contact layer. A contact hole is opened through the insulating film and the contact layer to reach the upper electrode. A metal interconnect, which is filled in the contact hole and connected to the upper electrode, is formed on a part of the insulating film.
摘要翻译：在基板上形成下电极，在下电极上由铁电体膜形成电容绝缘膜，在电容绝缘膜上形成上电极。接触层形成在上电极上。接触层是由金属氧化物或金属氮化物制成的单层膜或由金属氧化物和金属氮化物膜构成的多层结构。形成绝缘膜以覆盖下电极，电容绝缘膜，上电极和接触层。通过绝缘膜和接触层打开接触孔以到达上电极。填充在接触孔中并连接到上电极的金属互连件形成在绝缘膜的一部分上。

29. 发明授权

US06958508B2 Ferroelectric memory having ferroelectric capacitor insulative film 有权
标题翻译：具有铁电电容器绝缘膜的铁电存储器
公开(公告)号：US06958508B2
公开(公告)日：2005-10-25
申请号：US09968948
申请日：2001-10-03
申请人： Takumi Mikawa
发明人： Takumi Mikawa
IPC分类号： H01L21/02 , H01L21/285 , H01L21/768 , H01L21/8239 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L27/108
CPC分类号： H01L27/11509 , H01L21/28568 , H01L21/76895 , H01L27/105 , H01L27/1052 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/60 , H01L28/75
摘要： A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.
摘要翻译：电容器上电极和布线通过使用形成在电容元件下方的插塞和导电层而彼此电连接，而不使用通过其间的层间绝缘膜将电容器上电极直接连接到设置在其上的布线的插头。或者，电容器上电极被导电氢阻挡膜覆盖，并且电容器上电极和布线通过将布线和导电氢阻挡膜彼此连接的插塞彼此电连接，并且导电氢屏障电影。

30. 发明申请

US20050082637A1 Dielectric memory and method for fabricating the same 审中-公开
标题翻译：介质记忆及其制造方法
公开(公告)号：US20050082637A1
公开(公告)日：2005-04-21
申请号：US10964703
申请日：2004-10-15
申请人： Takumi Mikawa , Eiji Fujii
发明人： Takumi Mikawa , Eiji Fujii
IPC分类号： H01L21/02 , H01L21/314 , H01L21/316 , H01L21/768 , H01L21/8242 , H01L29/00
CPC分类号： H01L28/55 , H01L21/7687 , H01L28/56 , H01L28/65 , H01L28/75 , H01L28/91
摘要： A semiconductor device is provided with an insulating film which is formed on a semiconductor substrate and has a first recess, a capacitor lower electrode which is formed on the walls and the bottom of the first recess and has a second recess, and a capacitor insulating film which is formed on the walls and the bottom of the second recess and has a third recess, and a capacitor upper electrode embedded in the third recess.
摘要翻译：半导体器件设置有绝缘膜，该绝缘膜形成在半导体衬底上并且具有第一凹部，形成在第一凹部的壁和底部上并具有第二凹部的电容器下电极，以及电容器绝缘膜其形成在第二凹部的壁和底部上，并且具有第三凹部，以及嵌入在第三凹部中的电容器上电极。

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