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21. 发明授权

US5804858A Body contacted SOI MOSFET 失效
标题翻译：体接触SOI MOSFET
公开(公告)号：US5804858A
公开(公告)日：1998-09-08
申请号：US721667
申请日：1996-09-27
申请人： Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/336 , H01L29/786 , H01L27/01 , H01L29/76
CPC分类号： H01L29/66772 , H01L29/7841 , H01L29/78612 , H01L29/78621
摘要： A new method of forming a silicon-on-insulator device having a body node contact is described. Active areas are isolated from one another within a silicon-on-insulator layer. Adjacent active areas are doped with dopants of opposite polarities to form at least one n-channel active area and at least one p-channel active area. Gate electrodes are formed over each active area. The area directly underlying the gate electrode and extending downward to the insulator layer comprises the body node. Lightly doped areas are formed beneath the spacers on the sidewalls of the gate electrodes. First ions are implanted into the active areas not covered by a mask whereby source and drain regions are formed in the at least one n-channel active area and whereby a p-channel body contact region is formed within the at least one p-channel active area wherein the p-channel body contact region contacts the p-channel body node. Second ions are implanted into the active areas not covered by a mask whereby source and drain regions are formed in the at least one p-channel active area and whereby an n-channel body contact region is formed within the at least one n-channel active area wherein the n-channel body contact region contacts the n-channel body node. The semiconductor substrate is annealed to complete formation of the silicon-on-insulator device having a body node contact in the manufacture of an integrated circuit.
摘要翻译：描述了形成具有身体节点接触的绝缘体上硅器件的新方法。有源区域在绝缘体上硅层内彼此隔离。相邻有源区掺杂有相反极性的掺杂剂以形成至少一个n沟道有源区和至少一个p沟道有源区。在每个有效区域上形成栅电极。栅电极正下方并向下延伸至绝缘体层的区域包括主体节点。在栅电极的侧壁上的间隔物下方形成轻掺杂区域。将第一离子注入到未被掩模覆盖的有源区中，由此在至少一个n沟道有源区中形成源区和漏区，由此在至少一个p沟道活性区内形成p沟道体接触区其中所述p沟道体接触区域与所述p沟道体节点接触。将第二离子注入到未被掩模覆盖的有源区中，从而在至少一个p沟道有源区中形成源区和漏区，由此在至少一个n沟道活性区内形成n沟体体接触区其中所述n通道体接触区域与所述n通道体节点接触。半导体衬底被退火以在集成电路的制造中完成具有体节点接触的绝缘体上硅器件的形成。

22. 发明授权

US5693974A Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron MOSFETS 失效
标题翻译：用于深亚微米MOSFETs的固态扩散源极/漏极延伸的源极/漏极升高
公开(公告)号：US5693974A
公开(公告)日：1997-12-02
申请号：US606159
申请日：1996-02-23
申请人： Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/76 , H01L27/088 , H01L29/94
CPC分类号： H01L29/66628 , H01L21/823814 , H01L29/41783 , Y10S257/90
摘要： A semiconductor substrate is provided having n-channel and p-channel active areas separated by isolation areas. Gate electrodes are formed overlying a gate oxide layer over each of the active areas. First spacers are formed on the sidewalls of the gate electrodes wherein the first spacers have a first dopant concentration. The first spacers in the p-channel active area are removed and second spacers are formed on the sidewalls of the gate electrodes in the p-channel active area wherein the second spacers have a second dopant concentration different from the first dopant concentration. An epitaxial layer is grown on the surface of the semiconductor substrate wherein the epitaxial layer forms the elevated source/drain structure. First ions are implanted into the n-channel active area and second ions are implanted into the p-channel active area. The first and second ions are driven in to form heavily doped regions within the semiconductor substrate underlying the elevated source/drain structure. The driving in also drives in the first and second dopant concentrations of the first and second spacers to form source/drain extensions within the n-channel and p-channel active areas underlying the first and second spacers to complete the formation of the elevated source/drain structure with solid-phase diffused source/drain extensions in the manufacture of an integrated circuit.
摘要翻译：提供了具有被隔离区分隔开的n沟道和p沟道有源区的半导体衬底。在每个有效区域上形成覆盖栅极氧化物层的栅电极。第一间隔物形成在栅电极的侧壁上，其中第一间隔物具有第一掺杂剂浓度。除去p沟道有源区中的第一间隔物，并且在p沟道有源区中的栅电极的侧壁上形成第二间隔物，其中第二间隔物具有不同于第一掺杂剂浓度的第二掺杂剂浓度。在半导体衬底的表面上生长外延层，其中外延层形成升高的源/漏结构。第一离子注入n沟道有源区，第二离子注入p沟道有源区。驱动第一和第二离子以在升高的源极/漏极结构下面的半导体衬底内形成重掺杂区域。驱动还驱动第一和第二间隔物的第一和第二掺杂剂浓度，以在第一和第二间隔物下面的n沟道和p沟道有源区内形成源极/漏极延伸部分，以完成升高的源极/ 漏极结构，在集成电路的制造中具有固相扩散的源极/漏极延伸。

23. 发明授权

US5646435A Method for fabricating CMOS field effect transistors having sub-quarter micrometer channel lengths with improved short channel effect characteristics 失效
标题翻译：用于制造具有改进的短沟道效应特性的亚季度微米通道长度的CMOS场效应晶体管的方法
公开(公告)号：US5646435A
公开(公告)日：1997-07-08
申请号：US416168
申请日：1995-04-04
申请人： Charles Ching-Hsiang Hsu , Mong-Song Liang
发明人： Charles Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/423 , H01L29/45 , H01L29/76 , H01L21/265
CPC分类号： H01L29/66606 , H01L21/823412 , H01L29/0847 , H01L29/42376 , H01L29/456
摘要： A reverse self-aligned field effect transistor having sub-quarter micrometer (
摘要翻译：实现了具有二分之一微米（<0.25μm）沟道长度和浅源极/漏极结深度的反向自对准场效应晶体管。用于制造FET的方法包括在FET的源极/漏极区域上沉积和图案化的导电层。通过使用侧壁间隔物技术减小在导电层中形成的沟道开口来实现亚季度微米通道长度。衬底上的源极/漏极多晶硅层下面的导电层也用作与扩散源/漏极掺杂剂的界面，形成约0.06至0.08μm深度的浅结。导电层还用作与源极/漏极区域的低电阻欧姆接触。

24. 发明授权

US5591650A Method of making a body contacted SOI MOSFET 失效
标题翻译：使身体接触SOI MOSFET的方法
公开(公告)号：US5591650A
公开(公告)日：1997-01-07
申请号：US488683
申请日：1995-06-08
申请人： Ching-Hsiang Hsu , Mong-Song Liang
发明人： Ching-Hsiang Hsu , Mong-Song Liang
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265 , H01L21/225 , H01L21/385
CPC分类号： H01L29/66772 , H01L29/7841 , H01L29/78612 , H01L29/78621
摘要： A new method of forming a silicon-on-insulator device having a body node contact is dscribed. Active areas are isolated from one another within a silicon-on-insulator layer. Adjacent active areas are doped with dopants of opposite polarities to form at least one n-channel active area and at least one p-channel active area. Gate electrodes are formed over each active area. The area directly underlying the gate electrode and extending downward to the insulator layer comprises the body node. Lightly doped areas are formed beneath the spacers on the sidewalls of the gate electrodes. First ions are implanted into the active areas not covered by a mask whereby source and drain regions are formed in the at least one n-channel active area and whereby a p-channel body contact region is formed within the at least one p-channel active area wherein the p-channel body contact region contacts the p-channel body node. Second ions are implanted into the active areas not covered by a mask whereby source and drain regions are formed in the at least one p-channel active area and whereby an n-channel body contact region is formed within the at least one n-channel active area wherein the n-channel body contact region contacts the n-channel body node. The semiconductor substrate is annealed to complete formation of the silicon-on-insulator device having a body node contact in the manufacture of an integrated circuit.
摘要翻译：描述了形成具有身体节点接触的绝缘体上硅器件的新方法。有源区域在绝缘体上硅层内彼此隔离。相邻有源区掺杂有相反极性的掺杂剂以形成至少一个n沟道有源区和至少一个p沟道有源区。在每个有效区域上形成栅电极。栅电极正下方并向下延伸至绝缘体层的区域包括主体节点。在栅电极的侧壁上的间隔物下方形成轻掺杂区域。将第一离子注入到未被掩模覆盖的有源区中，由此在至少一个n沟道有源区中形成源区和漏区，由此在至少一个p沟道活性区内形成p沟道体接触区其中所述p沟道体接触区域与所述p沟道体节点接触。将第二离子注入到未被掩模覆盖的有源区中，从而在至少一个p沟道有源区中形成源区和漏区，由此在至少一个n沟道活性区内形成n沟体体接触区其中所述n通道体接触区域与所述n通道体节点接触。半导体衬底被退火以在集成电路的制造中完成具有体节点接触的绝缘体上硅器件的形成。

25. 发明授权

US5573961A Method of making a body contact for a MOSFET device fabricated in an SOI layer 失效
标题翻译：制造在SOI层中的MOSFET器件接触体的方法
公开(公告)号：US5573961A
公开(公告)日：1996-11-12
申请号：US565201
申请日：1995-11-09
申请人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
发明人： Ching-Hsiang Hsu , Shyh-Chyi Wong , Mong-Song Liang , Steve S. Chung
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： A process for fabricating a MOSFET device, on a silicon on insulator layer, in which a body contact to the silicon on insulator layer exists, has been developed. The process features creating a heavily doped P type body contact region in a lightly doped source and drain region of the MOSFET, via ion implantation through a metal silicide layer. The addition of the body contact results in more controllable device characteristics, in terms of drain currents, etc., than for counterparts fabricated in silicon on insulator layer, without the use of a body contact.
摘要翻译：已经开发了在绝缘体上硅层上制造MOSFET器件的方法，其中存在与绝缘体上硅层接触的物体。该工艺特征是通过金属硅化物层的离子注入在MOSFET的轻掺杂源极和漏极区域中产生重掺杂的P型体接触区域。身体接触的添加导致在漏极电流等方面比在绝缘体层上制造的对应物更不可控的器件特性，而不使用身体接触。

26. 发明授权

US08785272B2 Process to make high-K transistor dielectrics 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US08785272B2
公开(公告)日：2014-07-22
申请号：US13224059
申请日：2011-09-01
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/00 , H01L21/28 , H01L21/314
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

27. 发明授权

US08552522B2 Dishing-free gap-filling with multiple CMPs 有权
公开(公告)号：US08552522B2
公开(公告)日：2013-10-08
申请号：US13151666
申请日：2011-06-02
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/70
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

28. 发明授权

US08461629B2 Semiconductor device and method of fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08461629B2
公开(公告)日：2013-06-11
申请号：US13178755
申请日：2011-07-08
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

29. 发明授权

US08125051B2 Device layout for gate last process 有权
标题翻译：门最后进程的设备布局
公开(公告)号：US08125051B2
公开(公告)日：2012-02-28
申请号：US12471091
申请日：2009-05-22
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Mong-Song Liang , Hou-Ju Li , Ming-Yuan Wu , Tzung-Chi Lee
IPC分类号： H01L27/06 , H01L21/70 , H01L21/338 , H01L21/302
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0629 , H01L27/0635
摘要： A semiconductor device is provided that includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, an isolation structure formed in the second region, at least one junction device formed proximate the isolation structure in the second region, and a stopping structure formed overlying the isolation structure in the second region.
摘要翻译：提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，形成在第二区域中的隔离结构，形成在隔离结构中的至少一个接合器件第二区域，以及形成在第二区域中的隔离结构上方的停止结构。

30. 发明申请

US20120025329A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20120025329A1
公开(公告)日：2012-02-02
申请号：US13270585
申请日：2011-10-11
申请人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/78
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

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