专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20090051002A1 ELECTRICAL FUSE HAVING A THIN FUSELINK 失效
标题翻译：电子保险丝
公开(公告)号：US20090051002A1
公开(公告)日：2009-02-26
申请号：US11843047
申请日：2007-08-22
申请人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, JR. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.
摘要翻译：薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

22. 发明申请

US20090026491A1 TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE 有权
标题翻译：具有自对准门的隧道效应晶体管
公开(公告)号：US20090026491A1
公开(公告)日：2009-01-29
申请号：US11828740
申请日：2007-07-26
申请人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman
发明人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L29/70 , H01L21/33
CPC分类号： H01L29/7391 , H01L23/485 , H01L29/66356 , Y10S438/926 , Y10S438/979
摘要： In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.
摘要翻译：在一个实施例中，可以使用心轴和外部虚拟间隔件来形成第一导电类型区域。去除心轴以形成其中形成第二导电类型区域的凹陷区域。在另一个实施例中，心轴从浅沟槽隔离中移除以形成凹陷区域，其中形成内部虚拟间隔物。第一导电类型区域和第二导电区域形成在凹陷区域的其余部分内。进行退火，使得第一导电类型区域和第二导电类型区域通过扩散彼此邻接。栅电极形成为与第一和第二导电区域之间的p-n结自对准。由栅电极控制的可能是亚光刻的p-n结构成本发明的隧道效应晶体管。

23. 发明申请

US20110291166A1 INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR 有权
标题翻译：集成电路与FINFET和MIM FIN电容
公开(公告)号：US20110291166A1
公开(公告)日：2011-12-01
申请号：US12789013
申请日：2010-05-27
申请人： Roger A. Booth, JR. , Kangguo Cheng , Toshiharu Furukawa , Chengwen Pei
发明人： Roger A. Booth, JR. , Kangguo Cheng , Toshiharu Furukawa , Chengwen Pei
IPC分类号： H01L27/06 , H01L21/8242 , H01L21/02
CPC分类号： H01L27/0629 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L27/1211 , H01L28/91
摘要： An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.
摘要翻译：公开了一种具有finFET和金属 - 绝缘体 - 金属（MIM）鳍片电容器及其制造方法的集成电路。一种方法包括形成包括第一电介质和第一导体的第一finFET; 形成包括第二电介质和第二导体的第二finFET; 以及形成包括所述第一导体，所述第二电介质和所述第二导体的散热片电容器。

24. 发明申请

US20100230781A1 TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT 有权
标题翻译：用于可编程集成电路的抗融合结构
公开(公告)号：US20100230781A1
公开(公告)日：2010-09-16
申请号：US12537473
申请日：2009-08-07
申请人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
发明人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman , William R. Tonti
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.
摘要翻译：沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层沟槽的侧壁。电介质层设置在导电插塞和掺杂区域之间。电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

25. 发明申请

US20120061798A1 HIGH CAPACITANCE TRENCH CAPACITOR 有权
标题翻译：高电容式电容器
公开(公告)号：US20120061798A1
公开(公告)日：2012-03-15
申请号：US12881481
申请日：2010-09-14
申请人： Keich Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, JR.
发明人： Keich Kwong Hon Wong , Ramachandra Divakaruni , Roger A. Booth, JR.
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/40 , H01L27/10861 , H01L27/10867 , H01L29/945
摘要： A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.
摘要翻译：双节点介质沟槽电容器包括在沟槽中形成的一叠层。层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

26. 发明申请

US20120326270A1 INTERDIGITATED VERTICAL NATIVE CAPACITOR 有权
标题翻译：横向垂直电容器
公开(公告)号：US20120326270A1
公开(公告)日：2012-12-27
申请号：US13167076
申请日：2011-06-23
申请人： Eric Thompson , Roger A. Booth, JR. , Ning Lu , Christopher S. Putnam
发明人： Eric Thompson , Roger A. Booth, JR. , Ning Lu , Christopher S. Putnam
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L27/0207 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure.
摘要翻译：金属电容器结构包括与通孔层结构垂直相互连接的多个线路层结构。每个第一行级别结构和每个第二行级结构包括一组平行金属线，其在端部物理连接到具有矩形水平横截面积的矩形突片结构。第一线级结构内的第一组平行金属线和第二线级结构内的第二组平行金属线彼此交叉并且彼此平行，并且可以共同形成叉指的均匀间距结构。由于矩形凸片结构在矩形凸片结构的两个相对的侧壁之间的区域内不会朝向彼此突出，所以可以采用副分辨率辅助特征（SRAF）来提供在整个交叉的整体上的均匀的宽度和均匀的间距均匀节距结构。

27. 发明申请

US20120118619A1 BACK-END-OF-LINE PLANAR RESISTOR 失效
标题翻译：后端平面电阻器
公开(公告)号：US20120118619A1
公开(公告)日：2012-05-17
申请号：US12946294
申请日：2010-11-15
申请人： Roger A. Booth, JR. , Lawrence A. Clevenger
发明人： Roger A. Booth, JR. , Lawrence A. Clevenger
IPC分类号： H05K1/09 , H05K1/00 , H01L21/44
CPC分类号： H01L28/20 , H01L21/31116 , H01L21/31144 , H01L21/76808 , H01L21/76831 , H01L23/5228 , H01L23/5329 , H01L23/53295 , H01L28/24 , H01L2924/0002 , H01L2924/12044 , Y10T29/49082 , Y10T29/4913 , Y10T29/49155 , H01L2924/00
摘要： A stack of an interconnect-level dielectric material layer and a disposable dielectric material layer is patterned so that at least one recessed region is formed through the disposable dielectric material layer and in an upper portion of the interconnect-level dielectric material layer. A dielectric liner layer and a metallic liner layer is formed in the at least one recessed region. At least one photoresist is applied to fill the at least one recessed region and lithographically patterned to form via cavities and/or line cavities in the interconnect-level dielectric material layer. After removing the at least one photoresist, the at least one recessed region, the via cavities, and/or the line cavities are filled with at least one metallic material, which is subsequently planarized to form at least one planar resistor having a top surface that is coplanar with top surfaces of metal lines or metal vias.
摘要翻译：互连级介电材料层和一次性介电材料层的堆叠被图案化，使得通过一次性介电材料层和互连级介电材料层的上部形成至少一个凹陷区域。在所述至少一个凹部区域中形成介电衬垫层和金属衬垫层。施加至少一个光致抗蚀剂以填充至少一个凹陷区域并且被光刻图案化以在互连级介电材料层中形成通孔和/或线腔。在去除至少一个光致抗蚀剂之后，至少一个凹陷区域，通孔腔体和/或线腔体填充有至少一种金属材料，其随后被平坦化以形成至少一个具有顶表面的平面电阻器，与金属线或金属通孔的顶面共面。

28. 发明申请

US20090277670A1 High Density Printed Circuit Board Interconnect and Method of Assembly 审中-公开
标题翻译：高密度印刷电路板互连和组装方法
公开(公告)号：US20090277670A1
公开(公告)日：2009-11-12
申请号：US12118696
申请日：2008-05-10
申请人： Roger A. Booth, JR. , John R. Dangler , Matthew S. Doyle , Jesse M. Hefner , Thomas W. Liang , Ankur K. Patel , Paul W. Rudrud
发明人： Roger A. Booth, JR. , John R. Dangler , Matthew S. Doyle , Jesse M. Hefner , Thomas W. Liang , Ankur K. Patel , Paul W. Rudrud
IPC分类号： H05K1/02
CPC分类号： H05K1/142 , H05K3/325 , H05K3/365 , H05K2201/0314 , H05K2201/09845 , H05K2201/10378 , H05K2201/10598
摘要： A printed circuit board assembly having an edge joined first and second sub-circuit board is provided. The first sub-circuit board includes an edge with a stair-step profile interconnection wherein each of the stairs on the profile exposes an area of a signal layer. Each exposed portion of the signal layer has a plurality of signal pads thereon. The second sub-circuit board includes an edge with an inverse stair-step profile interconnection. A pad-on-pad connector is positioned in-between and electrically interconnects the respective signal layers on each sub-circuit board.
摘要翻译：提供了具有接合第一和第二子电路板的边缘的印刷电路板组件。第一子电路板包括具有阶梯轮廓互连的边缘，其中轮廓上的每个楼梯暴露信号层的区域。信号层的每个曝光部分在其上具有多个信号焊盘。第二子电路板包括具有逆阶梯轮廓互连的边缘。衬垫焊盘连接器位于每个子电路板之间并且电互连每个子电路板上的各个信号层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式