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    • 22. 发明授权
    • Hetergeneous method for determining module placement in FPGAs
    • 用于确定FPGA中模块放置的Hetergeneous方法
    • US06457164B1
    • 2002-09-24
    • US09608694
    • 2000-06-29
    • L. James HwangEric F. DellingerSujoy MitraSundararajarao MohanCameron D. PattersonRalph D. Wittig
    • L. James HwangEric F. DellingerSujoy MitraSundararajarao MohanCameron D. PattersonRalph D. Wittig
    • G06F1750
    • G06F17/5072
    • The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAS. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.
    • 本发明提供了在诸如FPGAS之类的可编程逻辑器件中使用的称为自实现模块(SIM)的参数模块。 本发明还提供了用于生成和使用SIM的工具和方法。 在设计时,SIMs实现自己,根据指定的参数对指定的FPGA进行定位。 在一个实施例中,SIM引用或包括一个或多个楼层布置器,每个楼层布置器可以采用一个或多个布置算法。 这样的放置算法可以包括例如:将数据路径逻辑按位地放置在规则线性模式中的线性排序算法; 在分布式RAM中实现网格图案中的存储器的矩形网格算法; 计数器和其他算术逻辑的柱状算法; 或用于诸如控制逻辑的随机逻辑的模拟退火算法。 因此,包括多于一个SIM的设计可以利用相同或不同层级的多个放置算法。 因此,整体设计可以利用不均匀的全球布局策略。
    • 23. 发明授权
    • Method for implementing wide gates and tristate buffers using FPGA carry logic
    • 使用FPGA进位逻辑实现宽门和三态缓冲器的方法
    • US06353920B1
    • 2002-03-05
    • US09193283
    • 1998-11-17
    • Ralph D. WittigSundararajarao MohanHamish T. Fallside
    • Ralph D. WittigSundararajarao MohanHamish T. Fallside
    • G06F1750
    • G06F7/501
    • A method for implementing wide gates and tristate buses using FPGA carry logic. Wide gate logic functions and tristate buses are detected and implemented with a plurality of LUTs and carry multiplexers. The wide gate functions are of the form: Ff=((( . . . (f0 $ f1) $ f2) $ f3) . . . ) $ fm, where $ represents a logic operator such as AND, OR or XOR. Thus the method includes the commonly used functions FAND=i1 AND i2 AND i3 AND . . . in; and FOR=i1 OR i2 OR i3 . . . in.as well as many mixed functions. The LUTs implement the respective portions of functions f0 through fm and the carry multiplexers implement the logic operators that connect the functions in a cascaded manner. A tristate bus definition includes a plurality of bus input signals and a plurality of bus select signals, each of the bus input signals associated with one or more of the bus select signals. The tristate bus is implemented by applying input and enable signals of the tristate bus to LUT input terminals, implementing inverted sum-of products of the input and enable signals and applying the output signals to the carry chain.
    • 一种使用FPGA进位逻辑实现宽门和三态总线的方法。 宽门逻辑功能和三态总线通过多个LUT进行检测和实现,并承载多路复用器。 宽门功能具有以下形式:其中$表示逻辑运算符,例如AND,OR或XOR。因此,该方法包括常用函数FAND = i1 AND i2 AND i3 AND。 。 。 在; FOR = i1 OR i2 OR i3。 。 。 和许多混合功能。 LUT实现函数f0至fm的相应部分,并且进位多路复用器实现以级联方式连接功能的逻辑运算符。 三态总线定义包括多个总线输入信号和多个总线选择信号,每个总线输入信号与一个或多个总线选择信号相关联。 通过将三态总线的输入和使能信号施加到LUT输入端子来实现三态总线,实现输入和使能信号的反相和产生,并将输出信号应用于进位链。
    • 25. 发明授权
    • Method for implementing large multiplexers with FPGA lookup tables
    • 使用FPGA查找表实现大型多路复用器的方法
    • US06191610B1
    • 2001-02-20
    • US09570808
    • 2000-05-15
    • Ralph D. WittigSundararajarao Mohan
    • Ralph D. WittigSundararajarao Mohan
    • G06F738
    • H03K19/17736H03K19/1737
    • A method for implementing a large multiplexer with FPGA lookup tables. Logic that defines a multiplexer is detected and implemented according to the number of inputs and the target FPGA architecture. In one situation, a large multiplexer is implemented in two stages. The first stage implements wide AND functions of each of the input signals using lookup tables and carry logic. In a second stage, the resulting decoded input signals are combined in a wide OR gate again formed from lookup tables and a carry chain. In another situation, the multiplexer is implemented as a tree structure using lookup tables that implement 2:1 multiplexers in combination with other 2:1 multiplexers provided by configurable logic blocks of the FPGA.
    • 一种实现具有FPGA查找表的大型多路复用器的方法。 根据输入数量和目标FPGA架构检测和实现定义多路复用器的逻辑。 在一种情况下,大的复用器分两个阶段实现。 第一阶段使用查找表和进位逻辑来实现每个输入信号的宽的AND函数。 在第二阶段中,所得到的解码输入信号被组合在由查找表和进位链再次形成的宽OR门中。 在另一种情况下,多路复用器被实现为使用查找表的树结构,其使用与由FPGA的可配置逻辑块提供的其他2:1多路复用器相结合的2:1多路复用器。
    • 27. 发明授权
    • Method for implementing large multiplexers with FPGA lookup tables
    • 使用FPGA查找表实现大型多路复用器的方法
    • US06505337B1
    • 2003-01-07
    • US09742277
    • 2000-12-19
    • Ralph D. WittigSundararajarao Mohan
    • Ralph D. WittigSundararajarao Mohan
    • G06F1750
    • H03K19/17736H03K19/1737H03K19/17728
    • A method for implementing a large multiplexer with FPGA lookup tables. Logic that defines a multiplexer is detected and implemented according to the number of inputs and the target FPGA architecture. In one situation, a large multiplexer is implemented in two stages. The first stage implements wide AND functions of each of the input signals using lookup tables and carry logic. In a second stage, the resulting decoded input signals are combined in a wide OR gate again formed from lookup tables and a carry chain. In another situation, the multiplexer is implemented as a tree structure using lookup tables that implement 2:1 multiplexers in combination with other 2:1 multiplexers provided by configurable logic blocks of the FPGA.
    • 一种实现具有FPGA查找表的大型多路复用器的方法。 根据输入数量和目标FPGA架构检测和实现定义多路复用器的逻辑。 在一种情况下,大的复用器分两个阶段实现。 第一阶段使用查找表和进位逻辑来实现每个输入信号的宽的AND函数。 在第二阶段中,所得到的解码输入信号被组合在由查找表和进位链再次形成的宽OR门中。 在另一种情况下,多路复用器被实现为使用查找表的树结构,其使用与由FPGA的可配置逻辑块提供的其他2:1多路复用器相结合的2:1多路复用器。
    • 28. 发明授权
    • Logic/memory circuit having a plurality of operating modes
    • 具有多个操作模式的逻辑/存储器电路
    • US06501296B2
    • 2002-12-31
    • US09912769
    • 2001-07-24
    • Ralph D. WittigSundararajarao MohanRichard A. Carberry
    • Ralph D. WittigSundararajarao MohanRichard A. Carberry
    • G06F738
    • H03K19/1776H03K19/1737H03K19/17728H03K19/17792
    • A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.
    • 具有读取模式和写入模式的存储器阵列使用单独的读取和写入解码器来寻址。 写解码器用于将位值写入阵列的一列。 利用硬接线读取解码器进一步提高存储器读取模式期间的操作速度。 在一个实施例中,提供单独的读取位线以便于更快的读取操作。 在示例性实施例中,写入解码器接收两个输入信号,并且在写入字线上产生四个写入地址信号,该写入字线被发送到逻辑/存储器阵列的可编程元件的列。 硬连线读取解码器还接收相同的两个输入信号,并且在两个读取字线上产生八个读取地址信号,两个读取地址信号被发送到逻辑/存储器阵列的每一列。
    • 29. 发明授权
    • Configurable logic element with expander structures
    • 具有扩展器结构的可配置逻辑元件
    • US06396302B2
    • 2002-05-28
    • US09860863
    • 2001-05-18
    • Bernard J. NewRalph D. WittigSundararajarao Mohan
    • Bernard J. NewRalph D. WittigSundararajarao Mohan
    • G06F738
    • H03K19/17748H03K19/1731H03K19/17728H03K19/17736H03K19/1776
    • A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.
    • 用于现场可编程门阵列(FPGA)的可配置逻辑元件(CLE)包括“扩展器”,即允许逻辑块之间的快速信号通信的连接器。 扩展器允许多个逻辑块或其部分的可配置互连形成可以实现诸如PAL,查找表,多路复用器,三态缓冲器和存储器之类的大型用户电路的单个逻辑实体。 一个实施例包括可配置逻辑块。 在第一模式中,逻辑块提供具有N个共享输入和两个单独输出的两个N输入LUT。 然后使用扩展器组合输出以产生(N + 1) - 输入功能。 在第二模式中,逻辑块提供具有M个非共享输入的两个N输入LUT。 可选的第三模式基于N个输入信号的值提供多个产品项输出信号。
    • 30. 发明授权
    • Heterogeneous method for determining module placement in FPGAs
    • 用于确定FPGA中模块放置的非均匀方法
    • US06243851B1
    • 2001-06-05
    • US09049892
    • 1998-03-27
    • L. James HwangEric F. DellingerSujoy MitraSundararajarao MohanCameron D. PattersonRalph D. Wittig
    • L. James HwangEric F. DellingerSujoy MitraSundararajarao MohanCameron D. PattersonRalph D. Wittig
    • G06F1750
    • G06F17/5072
    • The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.
    • 本发明提供了用于可编程逻辑器件(如FPGA)中的称为自实现模块(SIM)的参数模块。 本发明还提供了用于生成和使用SIM的工具和方法。 在设计时,SIMs实现自己,根据指定的参数对指定的FPGA进行定位。 在一个实施例中,SIM引用或包括一个或多个楼层布置器,每个楼层布置器可以采用一个或多个布置算法。 这样的放置算法可以包括例如:将数据路径逻辑按位地放置在规则线性模式中的线性排序算法; 在分布式RAM中实现网格图案中的存储器的矩形网格算法; 计数器和其他算术逻辑的柱状算法; 或用于诸如控制逻辑的随机逻辑的模拟退火算法。 因此,包括多于一个SIM的设计可以利用相同或不同层级的多个放置算法。 因此,整体设计可以利用不均匀的全球布局策略。