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1. 发明授权

US06260182B1 Method for specifying routing in a logic module by direct module communication 失效
标题翻译：通过直接模块通信在逻辑模块中指定路由的方法
公开(公告)号：US06260182B1
公开(公告)日：2001-07-10
申请号：US09049675
申请日：1998-03-27
申请人： Sundararajarao Mohan , Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Ralph D. Wittig
发明人： Sundararajarao Mohan , Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , G06F17/5054
摘要： The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM automatically places and interconnects child SIMs in a mesh pattern. The mesh is a 2-dimensional object corresponding to an array of CLBs on an FPGA. In essence, this embodiment allows a SIM to reserve routing resources on a target device (e.g., an FPGA), and allocate these resources to its child SIMs. Using a defined protocol, each child SIM can request and reserve routing resources, as well as placement resources (such as flip-flops and function generators in the CLBs) through the parent SIM. The routing resources are not necessarily limited to local or nearest neighbor routing.
摘要翻译：本发明提供了用于可编程逻辑器件（如FPGA）中的称为自实现模块（SIM）的参数模块。本发明还提供了用于生成和使用SIM的工具和方法。在设计时，SIMs实现自己，根据指定的参数对指定的FPGA进行定位。在一个实施例中，SIM自动地将网格图案中的子SIM放置并互连。网格是与FPGA上的CLB阵列相对应的二维对象。实质上，该实施例允许SIM在目标设备（例如，FPGA）上保留路由资源，并将这些资源分配给其子SIM。使用定义的协议，每个子SIM可以通过父SIM来请求和保留路由资源，以及布局资源（如CLB中的触发器和函数发生器）。路由资源不一定限于本地或最近邻居路由。

2. 发明授权

US06292925B1 Context-sensitive self implementing modules 失效
标题翻译：上下文敏感的自我实施模块
公开(公告)号：US06292925B1
公开(公告)日：2001-09-18
申请号：US09049891
申请日：1998-03-27
申请人： Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Sundararajarao Mohan , Ralph D. Wittig
发明人： Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Sundararajarao Mohan , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. SIMs are called “self implementing” because they encapsulate much of their own implementation information, including mapping, placement, and (optionally) routing information. Therefore, implementing a SIM-based design is significantly faster than with traditional modules, since much of the implementation is already complete and incorporated in the SIM.
摘要翻译：本发明提供了用于可编程逻辑器件（如FPGA）中的称为自实现模块（SIM）的参数模块。本发明还提供了用于生成和使用SIM的工具和方法。 SIM在设计时进行自己的设计，根据可能包括所需时序，数据宽度，FIR滤波器的抽头数等的指定参数来针对指定的FPGA。 SIM被称为“自我实施”，因为它们封装了大量自己的实现信息，包括映射，放置和（可选）路由信息。因此，实施基于SIM卡的设计比传统模块要快得多，因为大部分实现已经完成并被并入SIM卡中。

3. 发明授权

US06205574B1 Method and system for generating a programming bitstream including identification bits 失效
标题翻译：用于生成包括识别位的编程比特流的方法和系统
公开(公告)号：US06205574B1
公开(公告)日：2001-03-20
申请号：US09124464
申请日：1998-07-28
申请人： Eric F. Dellinger , Roman Iwanczuk
发明人： Eric F. Dellinger , Roman Iwanczuk
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： A method and system for generating a programming bitstream for a programmable gate array. A programming bitstream for the programmable gate array is generated in response to an input design specification. The programming bitstream includes one or more unused segments, either interspersed through the bitstream or appended to the end of the bitstream, wherein an unused segment includes bits that are not used for programming the programmable gate array. One or more selected items of information are encoded to form binary representations of the items. The binary representations are inserted into one or more of the unused segments of the programming bitstream.
摘要翻译：一种用于产生可编程门阵列的编程比特流的方法和系统。响应于输入设计规范生成用于可编程门阵列的编程比特流。编程比特流包括一个或多个未使用的片段，散布在比特流中或附加到比特流的末尾，其中未使用的片段包括不用于编程可编程门阵列的比特。一个或多个所选信息项被编码以形成项目的二进制表示。二进制表示被插入到编程比特流的一个或多个未使用的段中。

4. 发明授权

US06457164B1 Hetergeneous method for determining module placement in FPGAs 失效
标题翻译：用于确定FPGA中模块放置的Hetergeneous方法
公开(公告)号：US06457164B1
公开(公告)日：2002-09-24
申请号：US09608694
申请日：2000-06-29
申请人： L. James Hwang , Eric F. Dellinger , Sujoy Mitra , Sundararajarao Mohan , Cameron D. Patterson , Ralph D. Wittig
发明人： L. James Hwang , Eric F. Dellinger , Sujoy Mitra , Sundararajarao Mohan , Cameron D. Patterson , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAS. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.
摘要翻译：本发明提供了在诸如FPGAS之类的可编程逻辑器件中使用的称为自实现模块（SIM）的参数模块。本发明还提供了用于生成和使用SIM的工具和方法。在设计时，SIMs实现自己，根据指定的参数对指定的FPGA进行定位。在一个实施例中，SIM引用或包括一个或多个楼层布置器，每个楼层布置器可以采用一个或多个布置算法。这样的放置算法可以包括例如：将数据路径逻辑按位地放置在规则线性模式中的线性排序算法; 在分布式RAM中实现网格图案中的存储器的矩形网格算法; 计数器和其他算术逻辑的柱状算法; 或用于诸如控制逻辑的随机逻辑的模拟退火算法。因此，包括多于一个SIM的设计可以利用相同或不同层级的多个放置算法。因此，整体设计可以利用不均匀的全球布局策略。

5. 发明授权

US06243851B1 Heterogeneous method for determining module placement in FPGAs 失效
标题翻译：用于确定FPGA中模块放置的非均匀方法
公开(公告)号：US06243851B1
公开(公告)日：2001-06-05
申请号：US09049892
申请日：1998-03-27
申请人： L. James Hwang , Eric F. Dellinger , Sujoy Mitra , Sundararajarao Mohan , Cameron D. Patterson , Ralph D. Wittig
发明人： L. James Hwang , Eric F. Dellinger , Sujoy Mitra , Sundararajarao Mohan , Cameron D. Patterson , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters. In one embodiment, a SIM references or includes one or more floorplanners each of which may employ one or more placement algorithms. Such placement algorithms might include, for example: a linear ordering algorithm that places datapath logic bitwise in a regular linear pattern; a rectangular mesh algorithm that implements memory in a grid pattern in distributed RAM; a columnar algorithm for counters and other arithmetic logic; or a simulated annealing algorithm for random logic such as control logic. Therefore, a design including more than one SIM can utilize a plurality of placement algorithms at the same or different levels of hierarchy. The design as a whole can therefore utilize a non-uniform global placement strategy.
摘要翻译：本发明提供了用于可编程逻辑器件（如FPGA）中的称为自实现模块（SIM）的参数模块。本发明还提供了用于生成和使用SIM的工具和方法。在设计时，SIMs实现自己，根据指定的参数对指定的FPGA进行定位。在一个实施例中，SIM引用或包括一个或多个楼层布置器，每个楼层布置器可以采用一个或多个布置算法。这样的放置算法可以包括例如：将数据路径逻辑按位地放置在规则线性模式中的线性排序算法; 在分布式RAM中实现网格图案中的存储器的矩形网格算法; 计数器和其他算术逻辑的柱状算法; 或用于诸如控制逻辑的随机逻辑的模拟退火算法。因此，包括多于一个SIM的设计可以利用相同或不同层级的多个放置算法。因此，整体设计可以利用不均匀的全球布局策略。

6. 发明授权

US06237129B1 Method for constraining circuit element positions in structured layouts 失效
标题翻译：限制结构化布局中电路元件位置的方法
公开(公告)号：US06237129B1
公开(公告)日：2001-05-22
申请号：US09049598
申请日：1998-03-27
申请人： Cameron D. Patterson , Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Sundararajarao Mohan , Ralph D. Wittig
发明人： Cameron D. Patterson , Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Sundararajarao Mohan , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： The invention supplies a method whereby placement information for elements of a logic module is specified in such a manner that specific coordinates need not be included. This method can be applied to any module or other element having an associated placement in a programmable device. Using the method of the invention, relative coordinates (such as the RLOC constraints discussed in relation to the prior art) need not be specified. Instead, the invention introduces a vector-based form of layout. Key words or phrases such as “COLUMN” or “ROW” indicate the manner in which the elements of the module are to be placed. Use of such parametric words or phrases removes from the module developer the burden of determining exactly how large the module will be for each parameter combination, and in some cases finding expressions by which the relative locations can be calculated.
摘要翻译：本发明提供了一种方法，其中以不需要包括特定坐标的方式指定逻辑模块的元件的放置信息。该方法可以应用于在可编程设备中具有相关联的放置的任何模块或其他元件。使用本发明的方法，不需要指定相对坐标（例如关于现有技术讨论的RLOC约束）。相反，本发明引入了基于矢量的布局形式。诸如“COLUMN”或“ROW”的关键词或短语表示要放置模块的元素的方式。使用这样的参数词或短语从模块开发人员中删除确定每个参数组合的模块的准确程度的重要性，并且在某些情况下，找到可以计算相对位置的表达式。

7. 发明授权

US06216258B1 FPGA modules parameterized by expressions 失效
标题翻译： FPGA模块通过表达式进行参数化
公开(公告)号：US06216258B1
公开(公告)日：2001-04-10
申请号：US09049518
申请日：1998-03-27
申请人： Sundararajarao Mohan , Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Ralph D. Wittig
发明人： Sundararajarao Mohan , Eric F. Dellinger , L. James Hwang , Sujoy Mitra , Ralph D. Wittig
IPC分类号： G06F1750
CPC分类号： G06F17/5054
摘要： The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. In one embodiment, the SIM parameters may be symbolic expressions, which may comprise strings or string expressions, logical (Boolean) expressions, or a combination of these data types. The variables in these expressions are either parameters of the SIM or parameters of the “parent” of the SIM. Parametric expressions are parsed and evaluated at the time the SIM is elaborated; i.e., at run-time, usually when the design is mapped, placed, and routed in a specific FPGA. The use of parametric expressions interpreted at elaboration time allows dynamic inheritance and synthesis of actual parameter values, rather than the static value inheritance commonly found in programming languages such as C++ and Java.
摘要翻译：本发明提供了用于可编程逻辑器件（如FPGA）中的称为自实现模块（SIM）的参数模块。本发明还提供了用于生成和使用SIM的工具和方法。 SIM在设计时进行自己的设计，根据可能包括所需时序，数据宽度，FIR滤波器的抽头数等的指定参数来针对指定的FPGA。在一个实施例中，SIM参数可以是符号表达式，其可以包括字符串或字符串表达式，逻辑（布尔）表达式或这些数据类型的组合。这些表达式中的变量是SIM的参数或SIM的“父”的参数。参考表达式在SIM被详细阐述时被解析和评估; 即在运行时，通常当设计在特定的FPGA中进行映射，放置和路由时。在详细时间解释的参数表达式的使用允许实际参数值的动态继承和合成，而不是通常在编程语言（如C ++和Java）中发现的静态值继承。

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