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21. 发明授权

US06456522B1 Integrated memory having memory cells and buffer capacitors 有权
标题翻译：具有存储单元和缓冲电容器的集成存储器
公开(公告)号：US06456522B1
公开(公告)日：2002-09-24
申请号：US09953729
申请日：2001-09-17
申请人： Robert Feurle , Dominique Savignac
发明人： Robert Feurle , Dominique Savignac
IPC分类号： G11C700
CPC分类号： H01L29/66181 , H01L27/10805 , H01L27/10861 , H01L27/10897
摘要： An integrated memory includes memory cells each having a selector transistor and a storage capacitor. In each memory cell, the storage capacitor is connected to one of a plurality of column lines through the selector transistor, and a control terminal of the selector transistor is connected to one of a plurality of row lines. Buffer capacitors are each connected to a contact to another one of the column lines. The buffer capacitors are disposed in such a way that a connection between the respective buffer capacitor and the contact is disposed parallel to another one of the row lines. As a result, a permanently high dielectric strength is ensured through the use of the buffer capacitors.
摘要翻译：集成存储器包括各自具有选择晶体管和存储电容器的存储单元。在每个存储单元中，存储电容器通过选择晶体管连接到多条列线之一，并且选择晶体管的控制端连接到多行行之一。缓冲电容器各自连接到另一个列线的触点。缓冲电容器以这样的方式设置，使得各个缓冲电容器和触点之间的连接平行于另一条行线设置。结果，通过使用缓冲电容器确保了永久的高介电强度。

22. 发明授权

US06310399B1 Semiconductor memory configuration with a bit-line twist 有权
标题翻译：半导体存储器配置有位线扭曲
公开(公告)号：US06310399B1
公开(公告)日：2001-10-30
申请号：US09514268
申请日：2000-02-28
申请人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
发明人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
IPC分类号： H01L2348
CPC分类号： H01L27/10885 , H01L23/5225 , H01L27/10891 , H01L27/10897 , H01L2924/0002 , Y10S257/907 , H01L2924/00
摘要： A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane. The dummy contacts lead to the word-line plane to give the word lines a homogeneous environment. The further plane can be a word-line plane including the word lines. The bit lines in the twist-free area can be approximately from 150 nm to 250 nm wide, preferably 200 nm. The twist area can only include the twist of the bit lines. The bit lines in the twist area can be approximately from 250 nm to 350 nm wide, preferably, 330 nm wide. The bit lines can have spacing from 150 to 180 nm wide. The bit lines, the word lines, the contacts, and the dummy contacts can be made from copper or aluminum.
摘要翻译：半导体存储器配置包括位线平面中的位线，不同于位线平面的另一个平面，字线和与位线平面相邻的存储单元区域，一些位线沿着一条扭转位线中的其他位线被解捻，一些位线的对成对分别限定扭转位线对，扭转位线对具有用于使扭转位线对的一个位线交叉的触点扭转位线对的另一个位线和通过另一个平面的存储单元区域之后，未扭绞的其它位线具有从位线平面引导到另一个平面的虚拟触点。虚拟触点导致字线平面，使字线成为均匀的环境。另外的平面可以是包括字线的字线平面。无捻区域中的位线可以约为150nm至250nm宽，优选为200nm。扭曲区域只能包括位线的扭曲。扭转区域中的位线可以约为250nm至350nm宽，优选为330nm宽。位线可以具有150至180nm宽的间距。位线，字线，触点和虚拟触点可以由铜或铝制成。

23. 发明授权

US5546036A Circuit array for amplifying and holding data with different supply 失效
标题翻译：用于放大和保存不同电源的数据的电路阵列
公开(公告)号：US5546036A
公开(公告)日：1996-08-13
申请号：US376683
申请日：1995-01-23
申请人： Diether Sommer , Dominique Savignac , Dieter Gleis
发明人： Diether Sommer , Dominique Savignac , Dieter Gleis
IPC分类号： G11C7/06 , G11C7/10 , G11C11/4093 , H03K3/286
CPC分类号： G11C11/4093 , G11C7/065 , G11C7/1051
摘要： A circuit array for amplifying and holding data with different supply voltages includes a first flip-flop being constructed in MOS technology for receiving a low supply voltage and data with a low supply voltage. The first flip-flop has output terminals. A second flip-flop being constructed in MOS technology receives a high supply voltage. The second flip-flop has a load segment and output terminals. At least one additional MOS transistor is connected in series with each of the output terminals of the second flip-flop between the load segment and ground. The at least one additional MOS transistor each has a gate terminal being connected to a respective one of the output terminals of the first flip-flip. A device for activating the first and second flip-flops is triggered for amplifying and holding the data to activate the first flip-flop and to activate the second flip-flop after a time delay.
摘要翻译：用于放大和保持具有不同电源电压的数据的电路阵列包括以MOS技术构造的用于接收低电源电压的第一触发器和具有低电源电压的数据。第一个触发器具有输出端子。以MOS技术构造的第二个触发器接收高电源电压。第二个触发器具有负载段和输出端。至少一个额外的MOS晶体管与负载段和地之间的第二触发器的每个输出端串联连接。所述至少一个附加MOS晶体管的每个栅极端子连接到第一翻盖的输出端子的相应一个。触发用于激活第一和第二触发器的装置，用于放大和保持数据以激活第一触发器并在时间延迟之后激活第二触发器。

24. 发明申请

US20090039915A1 Integrated Circuit, Chip Stack and Data Processing System 失效
标题翻译：集成电路，芯片堆栈和数据处理系统
公开(公告)号：US20090039915A1
公开(公告)日：2009-02-12
申请号：US11834617
申请日：2007-08-06
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G11C5/04 , G11C5/02 , G11C7/10 , G11C29/1201 , G11C2029/0407 , H01L2224/16145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73257 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection and the memory circuit is deactivated.
摘要翻译：集成电路包括第一连接和存储电路。集成电路可以在其中第一连接和存储器电路之间的缓冲器被激活的主操作模式和从动操作模式之间切换，其中第一连接和存储器电路之间的缓冲器被停用。

25. 发明授权

US06654271B2 Method for reading and storing binary memory cells signals and circuit arrangement 有权
标题翻译：读取和存储二进制存储单元信号和电路布置的方法
公开(公告)号：US06654271B2
公开(公告)日：2003-11-25
申请号：US10152950
申请日：2002-05-21
申请人： Karl-Peter Pfefferl , Athanasia Chrysostomides , Dominique Savignac
发明人： Karl-Peter Pfefferl , Athanasia Chrysostomides , Dominique Savignac
IPC分类号： G11C502
CPC分类号： G11C7/18 , G11C7/10 , G11C2207/002
摘要： The invention features a method for reading and storing a binary memory cell signal where a signal transit time of the binary memory cell signal between one memory cell and an output terminal is reduced. The method includes applying a binary memory cell signal to a bit line pair; switching through the binary memory cell signal from the bit line pair to a local data line pair via a sense amplifier; switching through the amplified binary memory cell signal by a main data switching unit from the local data line to a main data line pair; and outputting the amplified, transferred binary memory cell signal via the first main data line and the second main data line pairs.
摘要翻译：本发明的特征在于一种用于读取和存储二进制存储单元信号的方法，其中一个存储单元和输出端之间的二进制存储单元信号的信号传输时间减少。该方法包括将二进制存储单元信号应用于位线对; 通过读出放大器将来自位线对的二进制存储单元信号切换到本地数据线对; 通过主数据交换单元从本地数据线切换到主数据线对的放大的二进制存储单元信号; 以及经由第一主数据线和第二主数据线对输出经放大的二进制存储单元信号。

26. 发明授权

US06586308B2 Method for producing circuit structures on a semiconductor substrate and semiconductor configuration with functional circuit structures and dummy circuit structures 有权
公开(公告)号：US06586308B2
公开(公告)日：2003-07-01
申请号：US09981856
申请日：2001-10-18
申请人： Sabine Kling , Dominique Savignac , Hans-Peter Moll , Henning Haffner , Elke Hietschold , Ines Anke
发明人： Sabine Kling , Dominique Savignac , Hans-Peter Moll , Henning Haffner , Elke Hietschold , Ines Anke
IPC分类号： H01L2120
CPC分类号： H01L27/0203 , H01L21/768 , H01L23/528 , H01L27/105 , H01L27/10894 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for producing circuit structures on a semiconductor substrate is described. Photoresist structures are formed, which define functional circuit structures and dummy circuit structures, whereby the dummy circuit structures which are smaller than a minimum structural size are joined to an additional second dummy circuit structure. The additional circuit structure is provided in such a way that the minimum structural size, which is determined by a smallest required joint surface of the photoresist on the substrate, is exceeded. A semiconductor circuit is also provided, which includes functional circuit structures and dummy circuit structures, the dummy circuit structures being joined to the additional dummy circuit structures.

27. 发明授权

US06426640B1 Semiconductor module for burn-in test configuration 失效
标题翻译：半导体模块，用于老化测试配置
公开(公告)号：US06426640B1
公开(公告)日：2002-07-30
申请号：US09440803
申请日：1999-11-15
申请人： Norbert Wirth , Eric Cordes , Zoltan Manyoki , Dominique Savignac
发明人： Norbert Wirth , Eric Cordes , Zoltan Manyoki , Dominique Savignac
IPC分类号： G01R3102
CPC分类号： G01R31/2856 , G01R31/2884
摘要： The invention relates to a semiconductor module for a burn-in test configuration. The semiconductor module has a regulator which, when it is turned on, always supplies a constant low voltage to an internal circuit of the semiconductor module. The semiconductor module also contains a component which, when the burn-in voltage has been applied for a defined time period, supplies a different characteristic than when the internal voltage is applied.
摘要翻译：本发明涉及一种用于老化测试配置的半导体模块。半导体模块具有调节器，当其导通时，总是向半导体模块的内部电路提供恒定的低电压。半导体模块还包含当在已经施加了预定时间段的老化电压时提供与施加内部电压不同的特性的组件。

28. 发明授权

US06256243B1 Test circuit for testing a digital semiconductor circuit configuration 有权
标题翻译：用于测试数字半导体电路配置的测试电路
公开(公告)号：US06256243B1
公开(公告)日：2001-07-03
申请号：US09642734
申请日：2000-08-17
申请人： Dominique Savignac , Wolfgang Nikutta , Michael Kund , Jan Ten Bröke
发明人： Dominique Savignac , Wolfgang Nikutta , Michael Kund , Jan Ten Bröke
IPC分类号： G11C700
CPC分类号： G11C29/36 , G11C29/26 , G11C29/34 , G11C29/38
摘要： A monolithically integrated test circuit for testing a digital semiconductor circuit configuration that is formed on the same semiconductor chip and has a large number of elements to be tested. The test circuit has a test data pattern register for temporary storage of a test data pattern, a read and write circuit for writing and reading the data in the test data pattern register to and from the elements to be tested, and a comparison circuit. The comparison circuit tests for any difference between the data written to and read from the elements to be tested. The test circuit has a pattern variation circuit, which can be activated by an activation signal and varies the test data pattern from the test data pattern register before writing into the elements to be tested.
摘要翻译：一种单片集成测试电路，用于测试形成在同一半导体芯片上并具有大量要测试元件的数字半导体电路配置。测试电路具有用于临时存储测试数据模式的测试数据模式寄存器，用于将测试数据模式寄存器中的数据写入和读取要测试的元件的读和写电路以及比较电路。比较电路测试写入和读取要测试元件的数据之间的任何差异。测试电路具有模式变化电路，其可以由激活信号激活，并且在写入要测试的元件之前从测试数据模式寄存器改变测试数据模式。

29. 发明授权

US5929491A Integrated circuit with ESD protection 失效
标题翻译：具有ESD保护的集成电路
公开(公告)号：US5929491A
公开(公告)日：1999-07-27
申请号：US9602
申请日：1998-01-20
申请人： Heinz Hebbeker , Werner Reczek , Dominique Savignac , Hartmud Terletzki
发明人： Heinz Hebbeker , Werner Reczek , Dominique Savignac , Hartmud Terletzki
IPC分类号： H01L27/02 , H01L23/62 , H01L29/00
CPC分类号： H01L27/0266
摘要： A parasitic field effect transistor or a parasitic diode is formed in an integrated circuit. The parasitic element is formed by two doped regions of the same or opposite conductivity type and an insulating region therebetween. The doped regions are each connected to a respective terminal pad of the integrated circuit. To increase the ESD strength, the length of the insulating region in the lateral direction is greater than or equal to a length of the longest discharge path of the ESD protection structures connected to the terminal pads.
摘要翻译：在集成电路中形成寄生场效应晶体管或寄生二极管。寄生元件由相同或相反导电类型的两个掺杂区域和它们之间的绝缘区域形成。掺杂区域各自连接到集成电路的相应的端子焊盘。为了增加ESD强度，绝缘区域在横向上的长度大于或等于连接到端子焊盘的ESD保护结构的最长放电路径的长度。

30. 发明授权

US5592063A Voltage generator circuit 失效
标题翻译：电压发生器电路
公开(公告)号：US5592063A
公开(公告)日：1997-01-07
申请号：US279918
申请日：1994-07-25
申请人： Dominique Savignac , Dieter Gleis , Manfred Menke
发明人： Dominique Savignac , Dieter Gleis , Manfred Menke
IPC分类号： G11C11/407 , G11C5/14 , G11C16/06 , H01L21/822 , H01L27/04 , G11C5/10
CPC分类号： G11C5/147 , G11C5/145
摘要： A voltage generator circuit includes a storage capacitor with a terminal for pickup of an output voltage. A voltage generator device which can be turned on and off has an output being connected to the terminal of the storage capacitor. A first comparator device which can be turned on and off compares the output voltage with a first threshold voltage and generates a signal for turning the voltage generator device on and off. A second comparator device compares the output voltage with a second threshold voltage and generates an output signal with which the first comparator device is turned on and off.
摘要翻译：电压发生器电路包括具有用于拾取输出电压的端子的存储电容器。可以接通和断开的电压发生器装置的输出端连接到存储电容器的端子。可以接通和关断的第一比较器装置将输出电压与第一阈值电压进行比较，并产生用于使电压发生器装置接通和关断的信号。第二比较器装置将输出电压与第二阈值电压进行比较，并产生与第一比较器装置接通和断开的输出信号。

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