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1. 发明授权

US06816432B2 Integrated semiconductor circuit having transistors that are switched with different frequencies 有权
标题翻译：具有以不同频率切换的晶体管的集成半导体电路
公开(公告)号：US06816432B2
公开(公告)日：2004-11-09
申请号：US10146582
申请日：2002-05-15
申请人： Robert Feurle , Dominique Savignac
发明人： Robert Feurle , Dominique Savignac
IPC分类号： G11C800
CPC分类号： H01L27/10873 , H01L21/823462 , H01L27/10894 , H01L27/10897
摘要： It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage. Therefore, semiconductor circuits having transistors with different operating voltages are provided with transistors having gate oxides of different thicknesses. This allows the gate oxide thickness to be influenced even more extensively. In this case, account is taken of the fact that infrequently addressed transistors, in particular memory transistors given the same gate oxide thickness, have a significantly longer lifetime than frequently switched transistors. An integrated semiconductor circuit having transistors whose gate oxide thicknesses are adapted to the switching frequency having different magnitudes, is proposed.
摘要翻译：已知以取决于工作电压的方式适应晶体管的尺寸，特别是局部栅极氧化物的层厚度。因此，具有不同工作电压的晶体管的半导体电路设置有具有不同厚度的栅极氧化物的晶体管。这允许栅极氧化物厚度更广泛地影响。在这种情况下，考虑到这样一个事实，即不常寻址的晶体管，特别是赋予相同栅极氧化物厚度的存储器晶体，具有比频率切换晶体管显着更长的寿命。提出了具有栅极氧化物厚度适应于具有不同幅度的开关频率的晶体管的集成半导体电路。

2. 发明授权

US06456522B1 Integrated memory having memory cells and buffer capacitors 有权
标题翻译：具有存储单元和缓冲电容器的集成存储器
公开(公告)号：US06456522B1
公开(公告)日：2002-09-24
申请号：US09953729
申请日：2001-09-17
申请人： Robert Feurle , Dominique Savignac
发明人： Robert Feurle , Dominique Savignac
IPC分类号： G11C700
CPC分类号： H01L29/66181 , H01L27/10805 , H01L27/10861 , H01L27/10897
摘要： An integrated memory includes memory cells each having a selector transistor and a storage capacitor. In each memory cell, the storage capacitor is connected to one of a plurality of column lines through the selector transistor, and a control terminal of the selector transistor is connected to one of a plurality of row lines. Buffer capacitors are each connected to a contact to another one of the column lines. The buffer capacitors are disposed in such a way that a connection between the respective buffer capacitor and the contact is disposed parallel to another one of the row lines. As a result, a permanently high dielectric strength is ensured through the use of the buffer capacitors.
摘要翻译：集成存储器包括各自具有选择晶体管和存储电容器的存储单元。在每个存储单元中，存储电容器通过选择晶体管连接到多条列线之一，并且选择晶体管的控制端连接到多行行之一。缓冲电容器各自连接到另一个列线的触点。缓冲电容器以这样的方式设置，使得各个缓冲电容器和触点之间的连接平行于另一条行线设置。结果，通过使用缓冲电容器确保了永久的高介电强度。

3. 发明授权

US06310399B1 Semiconductor memory configuration with a bit-line twist 有权
标题翻译：半导体存储器配置有位线扭曲
公开(公告)号：US06310399B1
公开(公告)日：2001-10-30
申请号：US09514268
申请日：2000-02-28
申请人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
发明人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
IPC分类号： H01L2348
CPC分类号： H01L27/10885 , H01L23/5225 , H01L27/10891 , H01L27/10897 , H01L2924/0002 , Y10S257/907 , H01L2924/00
摘要： A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane. The dummy contacts lead to the word-line plane to give the word lines a homogeneous environment. The further plane can be a word-line plane including the word lines. The bit lines in the twist-free area can be approximately from 150 nm to 250 nm wide, preferably 200 nm. The twist area can only include the twist of the bit lines. The bit lines in the twist area can be approximately from 250 nm to 350 nm wide, preferably, 330 nm wide. The bit lines can have spacing from 150 to 180 nm wide. The bit lines, the word lines, the contacts, and the dummy contacts can be made from copper or aluminum.
摘要翻译：半导体存储器配置包括位线平面中的位线，不同于位线平面的另一个平面，字线和与位线平面相邻的存储单元区域，一些位线沿着一条扭转位线中的其他位线被解捻，一些位线的对成对分别限定扭转位线对，扭转位线对具有用于使扭转位线对的一个位线交叉的触点扭转位线对的另一个位线和通过另一个平面的存储单元区域之后，未扭绞的其它位线具有从位线平面引导到另一个平面的虚拟触点。虚拟触点导致字线平面，使字线成为均匀的环境。另外的平面可以是包括字线的字线平面。无捻区域中的位线可以约为150nm至250nm宽，优选为200nm。扭曲区域只能包括位线的扭曲。扭转区域中的位线可以约为250nm至350nm宽，优选为330nm宽。位线可以具有150至180nm宽的间距。位线，字线，触点和虚拟触点可以由铜或铝制成。

4. 发明授权

US06528392B2 Dicing configuration for separating a semiconductor component from a semiconductor wafer 有权
标题翻译：用于从半导体晶片分离半导体部件的切割结构
公开(公告)号：US06528392B2
公开(公告)日：2003-03-04
申请号：US09745541
申请日：2000-12-21
申请人： Robert Feurle , Dominique Savignac
发明人： Robert Feurle , Dominique Savignac
IPC分类号： H01L2178
CPC分类号： H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： The dicing configuration for separating a semiconductor component from a semiconductor wafer is formed with a rupture joint which is created together with connecting holes that interconnect metallization planes, in a transition area between a scribe line and the semiconductor component. The rupture joint is an additional recess with which the insulating layer is made thinner.
摘要翻译：用于从半导体晶片分离半导体部件的切割结构形成有与切割线和半导体部件之间的过渡区域中连接金属化平面的连接孔一起形成的断裂接头。断裂接头是使绝缘层变薄的附加凹部。

5. 发明授权

US06426899B1 Integrated memory with a buffer circuit 有权
标题翻译：具有缓冲电路的集成存储器
公开(公告)号：US06426899B1
公开(公告)日：2002-07-30
申请号：US09594911
申请日：2000-06-15
申请人： Dominique Savignac , Robert Feurle , Helmut Schneider
发明人： Dominique Savignac , Robert Feurle , Helmut Schneider
IPC分类号： G11C700
CPC分类号： G11C11/4074 , G11C5/141 , H02J9/061
摘要： An integrated memory includes two potential nodes at which a supply voltage is present. Memory cells each have a selection transistor and a storage capacitor. At least one series circuit is disposed between the two potential nodes. The series circuits each have at least one buffer capacitor and one associated transistor. The associated transistor effects current limiting in the event of a defect in the at least one buffer capacitor. Each of the buffer capacitor and associated transistor have a mutual configuration and dimensions like the selection transistor and storage capacitor of one of the memory cells and have only an electrical connection differing from the selection transistor and storage capacitor.
摘要翻译：集成存储器包括存在电源电压的两个潜在节点。存储单元各自具有选择晶体管和存储电容器。在两个电位节点之间设置至少一个串联电路。串联电路各自具有至少一个缓冲电容器和一个相关联的晶体管。相关的晶体管在至少一个缓冲电容器的缺陷的情况下影响电流限制。缓冲电容器和相关晶体管中的每一个具有与存储单元之一的选择晶体管和存储电容器相互的配置和尺寸，并且仅具有与选择晶体管和存储电容器不同的电连接。

6. 发明授权

US06294841B1 Integrated semiconductor circuit having dummy structures 有权
标题翻译：具有虚拟结构的集成半导体电路
公开(公告)号：US06294841B1
公开(公告)日：2001-09-25
申请号：US09327699
申请日：1999-06-08
申请人： Dominique Savignac , Robert Feurle , Helmut Schneider
发明人： Dominique Savignac , Robert Feurle , Helmut Schneider
IPC分类号： H01L2348
CPC分类号： H01L23/5256 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： An integrated semiconductor circuit includes dummy structures. A portion of capacitive elements present in the dummy structures is used in order to adapt input/output parameters of pads of the integrated semiconductor circuit to an external line. Metal options, fuses or switches are suitable for the connection. The structure is neutral with respect to surface area.
摘要翻译：集成半导体电路包括虚拟结构。为了使集成半导体电路的焊盘的输入/输出参数适应于外部线路，使用存在于虚拟结构中的电容元件的一部分。金属选件，保险丝或开关适用于连接。该结构相对于表面积是中性的。

7. 发明授权

US06751145B2 Volatile semiconductor memory and mobile device 失效
标题翻译：易失性半导体存储器和移动设备
公开(公告)号：US06751145B2
公开(公告)日：2004-06-15
申请号：US10233968
申请日：2002-09-03
申请人： Robert Feurle , Dominique Savignac
发明人： Robert Feurle , Dominique Savignac
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： The volatile semiconductor memory is constructed from a plurality of memory segments. The information stored in the memory cells must be regularly reconditioned. Here, the time interval after the expiry of which the memory contents of the memory cells are reconditioned is set individually for each memory segment using corresponding subcircuits. The subcircuits receive, in a cyclical sequence, a refresh instruction. The passing on of the refresh instruction to the respective memory segment is interrupted if the segment-specific refresh time has not yet expired. This method of driving is implemented very easily and in a space-saving and cost-effective way in terms of circuitry.
摘要翻译：易失性半导体存储器由多个存储器段构成。存储在存储单元中的信息必须定期修复。这里，使用相应的子电路，针对每个存储器段分别对存储器单元的存储器内容进行再生的期满之后的时间间隔进行设置。子电路以周期性顺序接收刷新指令。如果片段特定的刷新时间尚未到期，则将刷新指令传递到相应的存储器段被中断。这种驾驶方法在电路方面非常容易地以节省空间和成本有效的方式实现。

8. 发明授权

US06441469B1 Semiconductor memory configuration with dummy components on continuous diffusion regions 有权
标题翻译：具有连续扩散区域上的虚拟部件的半导体存储器配置
公开(公告)号：US06441469B1
公开(公告)日：2002-08-27
申请号：US09511812
申请日：2000-02-24
申请人： Athanasia Chrysostomides , Robert Feurle , Dominique Savignac , Helmut Schneider
发明人： Athanasia Chrysostomides , Robert Feurle , Dominique Savignac , Helmut Schneider
IPC分类号： H01L23552
CPC分类号： H01L27/10897
摘要： The semiconductor memory configuration has at least two memory cell arrays. The open area between the strips of the sense-amp transistors in the two memory cell arrays contains dummy transistors. This avoids proximity effects at the edges of the sense-amp transistors adjoining the open area. The sense-amp transistors and the dummy transistors are arranged in a common, continuous diffusion region.
摘要翻译：半导体存储器配置具有至少两个存储单元阵列。两个存储单元阵列中的读出放大器晶体管的条带之间的开放区域包含虚拟晶体管。这避免了邻近开放区域的感测放大晶体管的边缘处的邻近效应。读出放大器晶体管和虚拟晶体管布置在共同的连续扩散区域中。

9. 发明授权

US06317378B1 Buffer circuit 有权
标题翻译：缓冲电路
公开(公告)号：US06317378B1
公开(公告)日：2001-11-13
申请号：US09592225
申请日：2000-06-12
申请人： Dominique Savignac , Robert Feurle , Helmut Schneider
发明人： Dominique Savignac , Robert Feurle , Helmut Schneider
IPC分类号： G11C514
CPC分类号： H03K19/017509 , G05F3/247
摘要： A buffer circuit serves for buffering a supply voltage of an integrated circuit. The supply voltage is present between two potential nodes. A series circuit is disposed between the two potential nodes and includes at least two buffer capacitors between which a third potential node is disposed. The third potential node is connected to an additional circuit which influences the potential of the third potential node in such a way that it does not exceed an upper and/or lower limit value when a leakage current occurs through one of the capacitors. The advantage of the buffer circuit is that when there is a defect in just one of the buffer capacitors, the other capacitor is prevented from being destroyed.
摘要翻译：缓冲电路用于缓冲集成电路的电源电压。电源电压存在于两个电位节点之间。串联电路设置在两个电位节点之间，并且包括至少两个缓冲电容器，第三电位节点之间设置有缓冲电容器。第三电位节点连接到附加电路，该附加电路以这样的方式影响第三电位节点的电位，使得当通过电容器之一发生漏电流时，其不超过上限值和/或下限值。缓冲电路的优点在于，当仅缓冲电容器中的一个存在缺陷时，防止另一电容器被破坏。

10. 发明授权

US08293431B2 Lithographic mask and method of forming a lithographic mask 有权
标题翻译：平版印刷掩模和形成光刻掩模的方法
公开(公告)号：US08293431B2
公开(公告)日：2012-10-23
申请号：US12761876
申请日：2010-04-16
申请人： Haiko Rolff , Carla Byloos , Christoph Noelscher , Nicolo Morgana , Roderick Koehle , Molela Moukara , Ralf Neubauer , Rainer Pforr , Dominique Savignac
发明人： Haiko Rolff , Carla Byloos , Christoph Noelscher , Nicolo Morgana , Roderick Koehle , Molela Moukara , Ralf Neubauer , Rainer Pforr , Dominique Savignac
IPC分类号： G03F1/40
CPC分类号： G03F1/40 , G03F1/26 , G03F1/30 , G03F1/32
摘要： A lithographic mask comprises a first layer including grooves, a second layer including regions, sections and a groove-like structure that encloses the sections. The first and second layers are formed so as to reduce electrical potential differences within the second layer. A method of forming a lithographic mask includes forming first and second layers to dispose the second layer over the first layer, patterning the second layer to comprise sections, a region, and a groove-like structure enclosing the sections, and forming grooves in the first layer at portions not covered by the second layer. The first and second layers are formed to reduce potential differences within the second layers during the step of forming the grooves in the first layer.
摘要翻译：平版印刷掩模包括包括凹槽的第一层，包含区域的第二层和包围区段的凹槽状结构。形成第一层和第二层以便减小第二层内的电位差。形成光刻掩模的方法包括形成第一层和第二层以将第二层设置在第一层上，将第二层图案化以包括封闭这些区段的区段，区域和沟槽状结构，以及在第一层中形成凹槽层在未被第二层覆盖的部分。形成第一层和第二层，以在形成第一层中的槽的步骤期间减小第二层内的电位差。

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