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1. 发明授权

US07379373B2 Voltage supply circuit, in particular for a DRAM memory circuit, as well as a method for controlling a supply source 有权
标题翻译：电压供应电路，特别是用于DRAM存储器电路，以及用于控制供应源的方法
公开(公告)号：US07379373B2
公开(公告)日：2008-05-27
申请号：US11295160
申请日：2005-12-05
申请人： Harald Lorenz , Manfred Menke , Helmut Seitz
发明人： Harald Lorenz , Manfred Menke , Helmut Seitz
IPC分类号： G11C5/14
CPC分类号： G11C11/4074 , G11C5/14
摘要： A voltage supply circuit for providing an internal supply voltage in an integrated circuit is provided. The voltage supply circuit comprises a supply source for setting the internal supply voltage on a supply voltage line and a control circuit which is connected to the supply source for switching on and off the supply source. The control circuit can itself be switched off and regularly switched on again, wherein the control circuit includes a control unit in order to switch the supply source on and off in such a way that the internal supply voltage on the supply voltage line differs essentially by no more than a limit value as a result of capacitive charge storage.
摘要翻译：提供了一种用于在集成电路中提供内部电源电压的电压供应电路。电压供给电路包括用于设定电源电压线上的内部电源电压的供给源和与供给源连接的用于接通和关闭供给源的控制电路。控制电路本身可以被断开并再次定期接通，其中控制电路包括一个控制单元，以便以这样的方式切换供电源，使得电源电压线上的内部电源电压基本上不变作为电容性电荷存储的结果，超过限制值。

2. 发明申请

US20050179461A1 Semiconductor memory circuit and method for operating the same in a standby mode 有权
标题翻译：半导体存储器电路及其在待机模式下的操作方法
公开(公告)号：US20050179461A1
公开(公告)日：2005-08-18
申请号：US11032535
申请日：2005-01-10
申请人： Manfred Menke , Esther Vega-Ordonez
发明人： Manfred Menke , Esther Vega-Ordonez
IPC分类号： G11C5/14 , G11C11/406 , G11C11/4074 , H03K19/003
CPC分类号： G11C11/40622 , G11C5/14 , G11C11/406 , G11C11/4074 , G11C2211/4067
摘要： A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power requirement, comprises an analog subcircuit having a power input and a signal output and is characterized by the fact that a switching device for feeding electrical power is connected to the power input and the controller is connected to the switching device in such a way that the switching device can be driven by the controller in such a way that the switching device, in the standby mode, supplies the analog subcircuit with electrical power during a first periodically repeated time duration and does not supply it with electrical power during a second periodically repeated time duration.
摘要翻译：一种具有控制器的半导体存储器电路，其中半导体存储器电路可以通过其降低功率需求而切换到待机模式，包括具有电源输入和信号输出的模拟子电路，其特征在于开关器件用于供电的电力被连接到电力输入端，并且控制器以这样的方式连接到开关装置，使得开关装置可以由控制器驱动，使得处于待机模式的开关装置提供模拟在第一周期性重复持续时间期间具有电力的分支电路，并且在第二周期性重复持续时间期间不提供电力。

3. 发明授权

US06909657B2 Pseudostatic memory circuit 失效
标题翻译：伪静态存储器电路
公开(公告)号：US06909657B2
公开(公告)日：2005-06-21
申请号：US10675433
申请日：2003-09-30
申请人： Andreas Jakobs , Thomas Janik , Manfred Menke , Eckehard Plättner
发明人： Andreas Jakobs , Thomas Janik , Manfred Menke , Eckehard Plättner
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40611
摘要： A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.
摘要翻译：通过存储器选择信号选择伪静态存储器电路。如果取消选择存储器电路，则在第一操作模式中的控制电路在接收到刷新请求信号之后的刷新地址处刷新存储器区域，或者如果在选择通过存储器选择信号的存储器电路，在生成另外的刷新请求信号之前结束对存储器区域的访问。在第二操作模式中，控制电路中断对存储器区域的访问以便写入和读出数据，并且如果选择了存储器电路，则通过产生刷新信号来进行存储区域的刷新在访问存储器区域的结束之前接收到刷新请求信号。

4. 发明申请

US20080113316A1 DENTAL IMPLANT FOR SUPPORTING A DENTAL PROSTHESIS 审中-公开
标题翻译：用于支持牙齿假体的牙科植入物
公开(公告)号：US20080113316A1
公开(公告)日：2008-05-15
申请号：US11876892
申请日：2007-10-23
申请人： Manfred Menke
发明人： Manfred Menke
IPC分类号： A61C8/00
CPC分类号： A61C8/0022 , A61C8/0018 , A61C8/005 , A61C8/006
摘要： Dental implant (10) for supporting a dental prosthesis on a jaw bone, is equipped with a main body (12), which comprises a securing portion (14) intended to be anchored in the bone tissue and, lying opposite it, a head portion (16). The head portion (16) protrudes radially beyond the securing portion (14) with respect to the longitudinal axis of the main body (12) to form a support face (26), in such a way that, in the state of insertion in the jaw bone, the pressure of the dental implant (10) on the jaw bone is reduced, and a sinking movement of the dental implant (10) into the jaw bone is effectively avoided, even over quite long periods of time.
摘要翻译：用于支撑颌骨上的牙科假体的牙种植体（10）装备有主体（12），该主体包括一个固定部分（14），该固定部分将被锚固在骨组织中，并且与其相对置，（16）。头部（16）相对于主体（12）的纵向轴线径向突出超过固定部分（14）以形成支撑面（26），使得在插入到主体颌骨上的牙植入物（10）的压力减小，并且即使在相当长的时间段内也能有效地避免牙植入物（10）进入颚骨的下沉运动。

5. 发明授权

US07356718B2 Semiconductor memory circuit and method for operating the same in a standby mode 有权
标题翻译：半导体存储器电路及其在待机模式下的操作方法
公开(公告)号：US07356718B2
公开(公告)日：2008-04-08
申请号：US11032535
申请日：2005-01-10
申请人： Manfred Menke , Esther Vega-Ordonez
发明人： Manfred Menke , Esther Vega-Ordonez
IPC分类号： G06F1/26
CPC分类号： G11C11/40622 , G11C5/14 , G11C11/406 , G11C11/4074 , G11C2211/4067
摘要： A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power requirement, comprises an analog subcircuit having a power input and a signal output and is characterized by the fact that a switching device for feeding electrical power is connected to the power input and the controller is connected to the switching device in such a way that the switching device can be driven by the controller in such a way that the switching device, in the standby mode, supplies the analog subcircuit with electrical power during a first periodically repeated time duration and does not supply it with electrical power during a second periodically repeated time duration.
摘要翻译：一种具有控制器的半导体存储器电路，其中半导体存储器电路可以通过其降低功率需求而切换到待机模式，包括具有电源输入和信号输出的模拟子电路，其特征在于开关器件用于供电的电力被连接到电力输入端，并且控制器以这样的方式连接到开关装置，使得开关装置可以由控制器驱动，使得处于待机模式的开关装置提供模拟在第一周期性重复持续时间期间具有电力的分支电路，并且在第二周期性重复持续时间期间不提供电力。

6. 发明申请

US20050179477A1 Integrated circuit and method for generating a ready signal 有权
标题翻译：用于产生就绪信号的集成电路和方法
公开(公告)号：US20050179477A1
公开(公告)日：2005-08-18
申请号：US11032536
申请日：2005-01-10
申请人： Manfred Menke
发明人： Manfred Menke
IPC分类号： G01R19/165 , H01L23/58 , H03K17/22 , H03L7/00
CPC分类号： H03K17/22 , G01R19/16552
摘要： An integrated circuit comprises an input for receiving a supply voltage, a field-effect transistor with a gate which is connected to the input in such a manner that the gate voltage present at the gate is a function of the supply voltage, a voltage source for generating a reference voltage which is connected to the input for receiving the supply voltage, a device for determining whether the gate voltage of the field effect transistor exceeds a turn-on voltage of the field-effect transistor, and a device for generating a ready signal which indicates that the supply voltage is high enough for performing functions of the integrated circuit, the device for generating being constructed for generating the ready signal when the gate voltage of the field-effect transistor exceeds the turn-on voltage of the field-effect transistor. The integrated circuit is characterized by the fact that a device for detecting the reference voltage generated by the voltage source is provided and the device for generating the ready signal is also constructed for generating the ready signal only when the reference voltage lies within a predetermined interval.
摘要翻译：集成电路包括用于接收电源电压的输入端，具有栅极的场效应晶体管，栅极连接到输入端，使得存在于栅极的栅极电压是电源电压的函数;电压源，产生连接到用于接收电源电压的输入的参考电压，用于确定场效应晶体管的栅极电压是否超过场效应晶体管的接通电压的装置，以及用于产生就绪信号的装置其指示电源电压足够高以用于执行集成电路的功能，当场效应晶体管的栅极电压超过场效应晶体管的接通电压时，用于产生的器件被构造用于产生就绪信号。集成电路的特征在于，提供用于检测由电压源产生的参考电压的装置，并且用于产生就绪信号的装置也被构造用于仅在参考电压处于预定间隔内时才产生就绪信号。

7. 发明授权

US06665224B1 Partial refresh for synchronous dynamic random access memory (SDRAM) circuits 有权
标题翻译：同步动态随机存取存储器（SDRAM）电路的部分刷新
公开(公告)号：US06665224B1
公开(公告)日：2003-12-16
申请号：US10153042
申请日：2002-05-22
申请人： Gunther Lehmann , Manfred Menke
发明人： Gunther Lehmann , Manfred Menke
IPC分类号： G11C700
CPC分类号： G11C11/40611 , G11C11/406 , G11C11/40622
摘要： A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of portions of the DRAM 300 to be refreshed, saving power and time over DRAMs that refresh the entire memory. The counter 345 may be programmed with a wordline address at the beginning of a block of memory and subsequent refresh operations automatically increment or decrement the value in the counter. Additionally, blocks of the memory not being refreshed can be accessed (written or read), improving the utilization of the memory device.
摘要翻译：提出了具有可编程存储器刷新计数器345的半导体动态随机存取存储器（DRAM）300。计数器345允许更新DRAM 300的部分的指定，从而节省了刷新整个存储器的DRAM的功率和时间。计数器345可以在存储器块的开始处用字线地址编程，并且随后的刷新操作自动地增加或减少计数器中的值。此外，可以访问（书写或读取）不刷新的存储器块，从而提高存储器件的利用率。

8. 发明授权

US06466493B1 Memory configuration having redundant memory locations and method for accessing redundant memory locations 有权
标题翻译：具有冗余存储器位置的存储器配置和用于访问冗余存储器位置的方法
公开(公告)号：US06466493B1
公开(公告)日：2002-10-15
申请号：US09690298
申请日：2000-10-17
申请人： Manfred Menke , Manfred Plan
发明人： Manfred Menke , Manfred Plan
IPC分类号： G11C700
CPC分类号： G11C29/78
摘要： A memory configuration is divided into memory blocks and allows a flexible access to redundant memory locations by using both, redundant column lines and redundant row lines of a particular memory block to repair defects of another memory block. Thus more defects can be repaired in the other memory block than there are redundant memory locations present in the other memory block. A method of accessing redundant memory locations is also provided. The memory configuration and the method of accessing redundant memory locations can be used in all memory architectures that write or read one or more bits of information per address in a parallel manner.
摘要翻译：存储器配置被分为存储器块，并且允许通过使用特定存储器块的冗余列线和冗余行线来灵活地访问冗余存储器位置，以修复另一个存储块的缺陷。因此，在另一个存储器块中可以修复其它存储器块中存在的冗余存储单元的更多缺陷。还提供了访问冗余存储器位置的方法。存储器配置和访问冗余存储器位置的方法可以用于以并行方式写入或读取每个地址的一个或多个位的信息的所有存储器架构。

9. 发明授权

US5796918A Method for ranking membership function values of linguistic input values in a fuzzy logic processor and arrangement for the implementation thereof 失效
标题翻译：用于对模糊逻辑处理器中的语言输入值的隶属函数值进行排序的方法及其实现方案
公开(公告)号：US5796918A
公开(公告)日：1998-08-18
申请号：US705865
申请日：1996-08-28
申请人： Manfred Menke
发明人： Manfred Menke
IPC分类号： G06F7/02 , G06F7/24 , G06F9/44 , G06N7/02 , G06N7/04 , G06G7/00
CPC分类号： G06F7/24 , G06N7/04 , Y10S706/90
摘要： An ordering method for ranking membership function values (Wi) of linguistic input values (LWEi) in a fuzzy logic processor is presented The steps of the method are: a) within the time of one processor clock, successively reading the membership function values (Wi) into holding elements (L1 . . . L4) and, after every reading, outputs of the holding elements are through-connected onto outputs (A . . . D) of a selector (SC) as determined by a selection signal (SEL); b) comparing the signals at the outputs (A . . . D) of the selector in comparators (C1,C2,C3) and generating control signals (S1 . . . S3) for a unit (SELC) which in turn generates the new selection signal (SEL); and c) writing pointers (MAX, MAX', MAX", MIN', MIN) into position registers (P1 . . . P5) with the assistance of the control signals (S1 . . . S3) such that the pointers enable a ranked access to the membership function values (Wi) in the holding elements (L1 . . . L4).
摘要翻译：提出了一种用于对模糊逻辑处理器中的语言输入值（LWEi）的隶属函数值（Wi）进行排序的排序方法。该方法的步骤是：a）在一个处理器时钟的时间内，连续读取隶属函数值（Wi ）到保持元件（L1 ... L4）中，并且在每次读取之后，保持元件的输出被连接到由选择信号（SEL）确定的选择器（SC）的输出（A ... D）上， ; b）将比较器（C1，C2，C3）中的选择器的输出（A ... D）上的信号与对于单元（SELC）产生控制信号（S1 ... S3）进行比较，该单元又产生新的选择信号（SEL）; 以及c）借助于控制信号（S1 ... S3）将指针（MAX，MAX'，MAX“，MIN'，MIN）写入位置寄存器（P1 ... P5），使得指针使能对保持元件（L1 ... L4）中的隶属函数值（Wi）进行分级访问。

10. 发明授权

US4026341A Two-part nut 失效
标题翻译：两部分坚果
公开(公告)号：US4026341A
公开(公告)日：1977-05-31
申请号：US640691
申请日：1975-12-15
申请人： Manfred Menke
发明人： Manfred Menke
IPC分类号： F16B37/06 , F16B39/00
CPC分类号： F16B37/064 , Y10S411/969
摘要： The two-part nut has a socket member and a member with an internally threaded shank and a flange which is received in a transverse groove in the socket member having a central bore traversed by the shank. The shank has a groove adjacent the flange into which reach upset portions of the socket member to hold the members together with play. The socket member has alternate bores for riveting.
摘要翻译：两部分螺母具有插座构件和具有内螺纹柄和凸缘的构件，该凸缘容纳在插座构件中的横向凹槽中，具有由该杆滑动的中心孔。柄部具有与凸缘相邻的凹槽，在该凹槽中，凹槽部分可伸入到插座构件的凹陷部分中，从而将构件保持在一起。插座构件具有用于铆接的备用孔。

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