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21. 发明专利

JP2005340862A Wiring substrate and its manufacturing method 有权
标题翻译：接线基板及其制造方法
公开(公告)号：JP2005340862A
公开(公告)日：2005-12-08
申请号：JP2005235209
申请日：2005-08-15
申请人： North:Kk , 株式会社ノース
发明人： IIJIMA ASAO
IPC分类号： H01L23/12
CPC分类号： H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/92247 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To increase the stiffness of a wiring substrate, further to abolish the need of fixing a stiffener by post-installation, and to easily enhance the positioning precision of the stiffener. SOLUTION: A first insulating layer 2 having an opening 3 is formed on a base 1 composed of metal, and one layer or multilayer wiring having a wiring film 5 is formed on the first insulating layer 2 including the opening 3. Further, a second insulating layer 6 having an opening 21 for forming a projective electrode in a wiring formation region is formed, and the stiffener 20 composed of the base 1 is formed by selectively etching the base 1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提高布线基板的刚度，进一步消除了通过后安装来固定加强件的需要，并且容易提高加强件的定位精度。解决方案：具有开口3的第一绝缘层2形成在由金属构成的基底1上，并且在包括开口3的第一绝缘层2上形成具有布线膜5的一层或多层布线。此外，形成具有用于在布线形成区域中形成突出电极的开口21的第二绝缘层6，并且通过选择性地蚀刻基底1而形成由基底1构成的加强件20.（C） JPO＆NCIPI

22. 发明专利

JP2005303133A Wiring board and its producing process 有权
标题翻译：接线板及其生产工艺
公开(公告)号：JP2005303133A
公开(公告)日：2005-10-27
申请号：JP2004119205
申请日：2004-04-14
申请人： North:Kk , 株式会社ノース
发明人： OHIRA HIROSHI , HARADA SATOSHI , IKENAGA KAZUO , ENDO KIMIYOSHI , IIJIMA ASAO
IPC分类号： H05K1/11 , H01L23/12 , H05K3/00 , H05K3/06 , H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To improve reliability in connection between the top surface of a metal bump and a wiring layer connected thereto, to improve yield of a wiring board, the wiring board using the metal bump as an interlayer connection means, and further to enhance electrical characteristics by enhancing an insulating part between wiring layers or between wiring boards. SOLUTION: The top surface of a metal bump 28 and a wiring film 10 (16) connected thereto are connected by direct metal bonding of metals, for example, copper-to-copper bonding. Furthermore, air or a foamed resin 12 containing air is used as an interlayer insulating film, Thus, reliability in the connection between the top surface of the metal bump and the wiring layer is improved, and yield of a wiring board can be enhanced. When interlayer insulation using air or the foamed resin is desired, the dielectric constant of an interlayer insulator is reduced to lower parasitic capacitance of the wiring circuit board or an electronic circuit using the same, thereby improving circuit characteristics and performance. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题为了提高金属凸块的上表面和与其连接的布线层之间的连接的可靠性，为了提高布线板的成品率，使用金属凸块作为层间连接装置的布线板，以及进一步通过增强布线层之间或布线板之间的绝缘部分来增强电特性。解决方案：通过金属的直接金属接合，例如铜 - 铜键合，金属凸块28的顶表面和与其连接的布线膜10（16）连接。此外，空气或含有空气的发泡树脂12用作层间绝缘膜。因此，金属凸块的顶表面与布线层之间的连接的可靠性得到改善，并且可以提高布线板的产量。当需要使用空气或发泡树脂的层间绝缘时，层间绝缘体的介电常数减小到降低布线电路板或使用其的电子电路的寄生电容，从而提高电路特性和性能。版权所有（C）2006，JPO＆NCIPI

23. 发明专利

JP2005252093A Interlayer insulating film for flexible printed wiring board, its manufacturing method, and flexible printed wiring board 审中-公开
标题翻译：柔性印刷线路板的绝缘膜绝缘膜及其制造方法和柔性印刷线路板
公开(公告)号：JP2005252093A
公开(公告)日：2005-09-15
申请号：JP2004062631
申请日：2004-03-05
申请人： North:Kk , Sony Chem Corp , Unitika Ltd , ソニーケミカル株式会社 , ユニチカ株式会社 , 株式会社ノース
发明人： ECHIGO YOSHIAKI , SHIGETA AKIRA , IIJIMA ASAO , OSAWA KENJI , ENDO KIMIYOSHI , KOBAYASHI KAZUYOSHI , HANAMURA KENICHIRO
IPC分类号： B32B27/34 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide an interlayer insulating film which can secure flatness as a flexible printed wiring board by making a thickness sufficiently thin as an interlayer insulating film, and improving wiring density of a multi-layered type flexible printed wiring plate along the thickness while securing adhesive strength for a circuit formation surface; and to provide electric, mechanical, and thermal reliability, and a flexible printed wiring board using the insulating film.
SOLUTION: The inter-layer insulating film is disclosed which has a 1st polyimide layer of 1 to 10 μm in thickness on one surface of a base film of 5 to 125 μm in thickness, and a 2nd polyimide layer of 10 to 50 μm in thickness on the other surface, and the flexible printed wiring board using the same insulating film. Further, a method is disclosed for manufacturing the same inter-layer insulating film that forms the 1st polyimide layer and 2nd polyimide layer by coating both the surfaces of the base film with a polyimide precursor solution and drying it, and then thermally making it into imide at temperature of 150 to 400°C.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种层间绝缘膜，其可以通过使厚度足够薄作为层间绝缘膜来确保作为柔性印刷布线板的平坦度，并且提高多层型柔性印刷布线板的布线密度沿着厚度同时固定电路形成表面的粘合强度; 并提供电气，机械和热可靠性，以及使用绝缘膜的柔性印刷线路板。解决方案：公开了层间绝缘膜，其具有厚度为5至125μm的基膜的一个表面上的厚度为1至10μm的第1聚酰亚胺层，第10聚酰亚胺层为10至50 另一个表面上的厚度为μm，使用相同绝缘膜的柔性印刷线路板。此外，公开了通过用聚酰亚胺前体溶液涂覆基膜的两面并干燥而形成第一聚酰亚胺层和第二聚酰亚胺层的相同层间绝缘膜的制造方法，然后将其热加成酰亚胺温度为150〜400℃。版权所有（C）2005，JPO＆NCIPI

24. 发明专利

JP2005005739A Wiring circuit board and manufacturing method therefor 有权
标题翻译：接线电路板及其制造方法
公开(公告)号：JP2005005739A
公开(公告)日：2005-01-06
申请号：JP2004273404
申请日：2004-09-21
申请人： North:Kk , 株式会社ノース
发明人： IIJIMA ASAO , OSAWA MASAYUKI
IPC分类号： H05K3/40 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To form an alignment mark (identification mark) required for location alignment necessary for the manufacturing process of an wiring circuit board, without increasing the number of processes; further, make misregistration between the identity mark and a projection be smaller in the interconnect circuit substrate in which the projection for connection between upper/lower conductors, consisting of many metals, is arranged on the surface of metallization layer; layer-to-layer insulating layer is formed on front surface formed by the projection for the connection between upper/lower conductors of the metallization layer, in such a state that it is penetrated by the projection for connection between upper/lower conductors, and metallization layers consisting of the metallization layer are formed on front surface including the projection for connection between upper/lower conductors of the layer-to-layer insulating layer, or its manufacturing method.
SOLUTION: The board has an identification mark 63, formed by the same material and to the same height as those of the projections for connection between upper/lower conductors 53, 57, and the projections for connection between upper/lower conductors 53, 57 and the identification mark 63 are formed in the same process.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了形成布线电路板的制造过程所需的位置对准所需的对准标记（识别标记），而不增加处理次数; 此外，在互连电路基板中，在由多种金属组成的上/下导体之间的连接用突起布置在金属化层的表面上，使得识别标记与突起之间的配准更小; 在由金属化层的上/下导体之间的连接用突起形成的前表面上形成有层间绝缘层，在被上下导体之间连接用突起部穿透的状态下，由金属化层组成的层形成在包括用于在层间绝缘层的上/下导体之间连接的突起的前表面上，或其制造方法。解决方案：板具有由与上/下导体53,57之间连接的突起和用于连接上/下导体53之间的突起的材料相同的高度和相同的高度形成的识别标记63 ，57和识别标记63以相同的方法形成。版权所有（C）2005，JPO＆NCIPI

25. 发明专利

JP2004342877A Method of connecting metals and method of mounting electronic component 审中-公开
公开(公告)号：JP2004342877A
公开(公告)日：2004-12-02
申请号：JP2003138457
申请日：2003-05-16
申请人： Dept Corp , North:Kk , デプト株式会社 , 株式会社ノース
发明人： UENO TAKASHI , IIJIMA ASAO , ENDO KIMIYOSHI , OHIRA HIROSHI
IPC分类号： H05K3/32 , H01L21/60
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a method of connecting metals which requires no heating nor pressurization, and to provide a method of mounting electronic components.
SOLUTION: The method of connecting metals comprises a step of preparing bumps 1 and 2 which are formed of Cu or Cu alloy, disposing a conductive auxiliary film 3 between the bumps 1 and 2, and applying voltage between the bumps 1 and 2 to connect them. It is preferred that the conductive auxiliary film 3 is a film formed of a polymeric material, and that the voltage applied between the bumps 1 and 2 is 0.5-10 V.
COPYRIGHT: (C)2005,JPO&NCIPI

26. 发明专利

JP2005285849A Interlayer member for manufacturing multilayer wiring board and its manufacturing method 审中-公开
标题翻译：制造多层布线板的层间成员及其制造方法
公开(公告)号：JP2005285849A
公开(公告)日：2005-10-13
申请号：JP2004093693
申请日：2004-03-26
申请人： North:Kk , 株式会社ノース
发明人： OSAWA KENJI , OSAWA MASAYUKI , SHIMADA TOMOKAZU , ENDO KIMIYOSHI , IIJIMA ASAO
IPC分类号： H01L21/4763 , H01L21/48 , H01L21/60 , H01L23/50 , H05K1/11 , H05K1/16 , H05K3/40 , H05K3/42 , H05K3/46
CPC分类号： H05K3/4614 , H01L2924/0002 , H05K3/423 , H05K3/4647 , H05K2201/0355 , H05K2201/10378 , H05K2203/0384 , H05K2203/0726 , H05K2203/0733 , H05K2203/1152 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve disposition density by enhancing the accuracy of the size of an interlayer member for manufacturing a multilayer wiring board interposed between two wiring layers for ensuring interlayer insulation between the wiring layers and interlayer electrical connection. SOLUTION: A mask film 4 is formed on the principal surface of a sheet-shaped carrier layer 2, and a metal post 8 for interlayer connection is formed on the principal surface of the carrier layer 2 by plating copper with the mask film 4 used as a mask. Then, the mask 4 is removed, and an interlayer insulating layer 10 and a protective sheet 12 are stacked on the principal surface of the carrier layer 2 so as to permit it to be penetrated by the metal post 8 for interlayer connection, and the upper surface of the metal post 8 for interlayer connection is exposed beyond the interlayer insulating layer 10 and the protective sheet 12. Thereafter, the carrier layer is removed, and the protective sheet 12 is also removed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：通过提高用于制造布线在两个布线层之间的多层布线板的层间构件的尺寸的精度来提高布置层的密度，以确保布线层之间的层间绝缘和层间电连接。解决方案：在片状载体层2的主表面上形成掩模膜4，在载体层2的主表面上通过用掩模膜电镀铜形成层间连接用金属柱8 4用作面具。然后，去除掩模4，并且在载体层2的主表面上堆叠层间绝缘层10和保护片12，以允许其穿过用于层间连接的金属柱8，并且上层用于层间连接的金属柱8的表面暴露在层间绝缘层10和保护片12之外。此后，移除载体层，并且还去除保护片12。版权所有（C）2006，JPO＆NCIPI

27. 发明专利

JP2005223056A Printed wiring board and its manufacturing method 有权
标题翻译：印刷线路板及其制造方法
公开(公告)号：JP2005223056A
公开(公告)日：2005-08-18
申请号：JP2004028083
申请日：2004-02-04
申请人： Fujikura Ltd , North:Kk , 株式会社ノース , 株式会社フジクラ
发明人： SAKAI CHIKARA , UNAMI YOSHIHARU , SAKIYAMA FUJIO , INATANI YASUSHI , IIJIMA ASAO , OSAWA KENJI
IPC分类号： H05K1/11 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To improve the adhesive properties of an insulating base layer and a conductor circuit by complementing a close adhesion between an insulating layer (the insulating base layer) and the conductor circuit.
SOLUTION: In a printed-wiring board (30), a first metallic layer (11) in which a plurality of conductive bumps (14 and 15) are formed on one surface, and a second metallic layer (17) are superposed while holding the insulating layer (16) arranged in regions excepting each bump (14 and 15), and the tops (14A and 15A) of each bump (14 and 15) and the second metallic layer (17) are connected. The printed-wiring board has one or more of the bumps (15) for reinforcement.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过补充绝缘层（绝缘基底层）和导体电路之间的紧密粘附来改善绝缘基底层和导体电路的粘合性能。解决方案：在印刷电路板（30）中，在一个表面上形成有多个导电凸块（14和15）的第一金属层（11）和第二金属层（17）重叠同时保持布置在除了每个凸块（14和15）之外的区域中的绝缘层（16），并且每个凸块（14和15）和第二金属层（17）的顶部（14A和15A）连接。印刷电路板具有一个或多个用于加强的凸块（15）。版权所有（C）2005，JPO＆NCIPI

28. 发明专利

JP2005123269A Wiring board and its manufacturing method 有权
标题翻译：接线板及其制造方法
公开(公告)号：JP2005123269A
公开(公告)日：2005-05-12
申请号：JP2003354053
申请日：2003-10-14
申请人： North:Kk , 株式会社ノース
发明人： IIJIMA ASAO
IPC分类号： G02F1/1345 , H05K1/11 , H05K3/18 , H05K3/40 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To achieve much more microfabrication and much higher integration of a wiring film 16 of a wiring board 2 while assuring reliability. SOLUTION: On at least one surface of the board 2, a pattern thin film 12 is to be formed in a predetermined pattern with metallic particles or metal oxide particles of nano meter scale with mean particle diameter as 1-100 nm. The film 12 is formed as a mother film by using an ink jet method, a dispenser, screen-stencil, etc., and dried. Solvent etc. are vaporized. By heating (150-250°C) of the film 12, the metallic particles (objects in which the metal oxide particles are turned into metallic particles by reduction are contained) are bonded to each other, melting is performed, and a metal film 14 is formed on the pattern thin film 12 which constitutes the mother film. The wiring film 16 is constituted of the metal plating film 14 and the pattern thin film 12 as the mother film of the film 14. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在确保可靠性的同时，实现布线板2的布线膜16的微细化加工和更高集成度。解决方案：在板2的至少一个表面上，图案薄膜12将以具有1-100nm的平均粒径的纳米级的金属颗粒或金属氧化物颗粒以预定图案形成。通过使用喷墨法，分配器，筛网模板等将膜12形成为母膜并干燥。溶剂等蒸发。通过加热（150-250℃）薄膜12，金属颗粒（包含金属氧化物颗粒通过还原而变成金属颗粒的物体）彼此结合，进行熔融，并且金属膜14 形成在构成母膜的图案薄膜12上。布线膜16由金属镀膜14和作为膜14的母膜的图案薄膜12构成。版权所有（C）2005，JPO＆NCIPI

29. 发明专利

JP2005085930A Flexible wiring board and its manufacturing method 有权
标题翻译：柔性接线板及其制造方法
公开(公告)号：JP2005085930A
公开(公告)日：2005-03-31
申请号：JP2003315283
申请日：2003-09-08
申请人： North:Kk , 株式会社ノース
发明人： IIJIMA ASAO , MITSUNARI NAOHITO
IPC分类号： H05K1/02 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a flexible wiring board which hardly causes separation between interconnections and an insulation film when being bent and has little extrusion in bending parts, and to provide its manufacturing method.
SOLUTION: As shown in (e), resist is applied and is then exposed at two parts between bumps 104 using an exposure mask having a prescribed pattern. Thereafter, the exposed parts of the resist are moved by a development process to form a resist mask 107. Next, as shown in (f), the insulation film 106 is etched to a prescribed thickness with the resist mask 107 as a mask, forming two thin portions 108 in the insulation film 106. These thin portions 108 correspond to the bending parts at the time of bending the flexible wiring board in an after-process (semiconductor package lamination process).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种柔性布线板，其在弯曲时几乎不会导致互连和绝缘膜之间的分离，并且弯曲部分的挤压少，并且提供其制造方法。解决方案：如（e）所示，施加抗蚀剂，然后使用具有规定图案的曝光掩模在凸块104之间的两部分处曝光。此后，通过显影处理移动抗蚀剂的曝光部分以形成抗蚀剂掩模107.接下来，如（f）所示，用抗蚀剂掩模107作为掩模将绝缘膜106蚀刻至规定厚度，形成绝缘膜106中的两个薄部分108.这些薄部分108对应于在后处理（半导体封装层压工艺）中弯曲柔性布线板时的弯曲部分。版权所有（C）2005，JPO＆NCIPI

30. 发明专利

JP2005026458A Wiring board with built-in functional element 审中-公开
标题翻译：具有内置功能元件的接线板
公开(公告)号：JP2005026458A
公开(公告)日：2005-01-27
申请号：JP2003190342
申请日：2003-07-02
申请人： North:Kk , 株式会社ノース
发明人： IIJIMA ASAO , FUKUOKA YOSHITAKA
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board having high mounting density by disposing stereoscopically a semiconductor integrated circuit element and passive functional elements embedded in the multilayer circuit board.
SOLUTION: The multilayer wiring board with built-in functional element includes a rigid wiring part A made, for example, of six layers, which contains, in addition to the passive functional elements, such as a resistor R, a capacitor C, an inductor L, etc., the passive functional element, such as an LSI chip 81, etc. formed in thickness of 50 μm or less by polishing a rear surface. Also, in a flexible wiring part B made, for example, of two layers, an LSI chip 82 formed in thickness of 50 μm or less by polishing its rear surface is similarly contained. The wiring parts A, B become a continued integral multilayer wiring board. Thus, this can be applied to applications of a wide range required for the high mounting density and flexibility.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决方案：通过立体地配置半导体集成电路元件和嵌入在多层电路板中的无源功能元件，提供具有高安装密度的多层布线板。解决方案：具有内置功能元件的多层布线板包括例如六层制成的刚性布线部分A，除了诸如电阻器R的无源功能元件之外，电容器C ，电感器L等，通过抛光后表面而形成厚度为50μm以下的无源功能元件，例如LSI芯片81等。此外，在例如由两层制成的柔性布线部分B中，类似地包含通过抛光其后表面形成厚度为50μm以下的LSI芯片82。布线部分A，B成为连续整体的多层布线板。因此，这可以应用于高安装密度和柔性所需的宽范围的应用。版权所有（C）2005，JPO＆NCIPI

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