会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 22. 发明授权
    • Overshoot current phase/amplitude control for hard disk drive write current
    • 过冲电流相位/幅度控制硬盘驱动器写入电流
    • US06870697B2
    • 2005-03-22
    • US10457473
    • 2003-06-10
    • Hiroshi IkekameTakeo Yamashita
    • Hiroshi IkekameTakeo Yamashita
    • G11B5/09G11B5/00G11B5/012G11B5/02G11B20/10
    • G11B5/012G11B5/02G11B20/10009G11B2005/0013
    • Devices and methods for generating a magnetic head-specific overshoot current which is combined with an alternating current waveform into a write current used by the magnetic head to store information on a magnetic medium. A processor analyzes the frequency of incoming write data and retrieves from a data table of an overshoot current amplitude and an overshoot current phase. This amplitude and phase information is sent to an overshoot current generator to generate an overshoot current that is responsive to the dynamic impedance properties of a magnetic write head during operation. The data table may have information related to one or many write heads, and the data table may be further subdivided based on additional dynamic characteristics of a write head that may affect the impedance thereof.
    • 用于产生磁头特定过冲电流的装置和方法,其将交流电波组合成由磁头用于在磁介质上存储信息的写入电流。 处理器分析输入写入数据的频率,并从数据表中检索过冲电流幅度和过冲电流相位。 该幅度和相位信息被发送到过冲电流发生器以产生响应于操作期间磁写头的动态阻抗特性的过冲电流。 数据表可以具有与一个或多个写入头相关的信息,并且可以基于可能影响其阻抗的写入头的附加动态特性来进一步细分数据表。
    • 24. 发明授权
    • Semiconductor devices utilizing silicide reaction
    • 利用硅化物反应的半导体器件
    • US6051851A
    • 2000-04-18
    • US917675
    • 1997-08-26
    • Tadahiro OhmiMamoru MiyawakiYoshio NakamuraHiroshi SuzukiTakeo Yamashita
    • Tadahiro OhmiMamoru MiyawakiYoshio NakamuraHiroshi SuzukiTakeo Yamashita
    • H01L21/82G11C17/16H01L23/525H01L27/10H01L31/0328H01L31/0336H01L31/072H01L31/109
    • H01L27/112G11C17/16H01L23/5252H01L27/11206H01L2924/0002H01L2924/3011
    • Cheap semiconductor memory devices are provided so as to enable high-speed writing and reading but rarely to malfunction, thus being high in reliability. In a semiconductor device which comprises a plurality of cells each having a semiconductor layer between a pair of conductors, at least one of the pair of conductors is made of a metal, and the semiconductor layer comprises an amorphous silicon that can form a silicide region with the metal as reacting at a reaction rate of not less than 10 m/sec. Another device is characterized in that the semiconductor layer is an amorphous silicon, in that at least one of the pair of conductors is made of a metal silicide-reacting with the amorphous silicon, and in that the silicide region formed is conic. Another device is characterized in that the semiconductor layer is an amorphous silicon, in that at least one of the pair of conductors is formed of a metal silicide-reacting with the amorphous silicon, and in that a film-formed surface is produced without being exposed to an oxide atmosphere, between a step of forming the amorphus silicon and a step of forming the metal.
    • 提供廉价的半导体存储器件,以便能够进行高速写入和读取,但很少发生故障,因此可靠性高。 在包括多个单元的半导体器件中,每个单元各自在一对导体之间具有半导体层,所述一对导体中的至少一个导体由金属制成,并且所述半导体层包括可形成硅化物区域的非晶硅, 金属以不小于10m /秒的反应速率反应。 另一种器件的特征在于,半导体层是非晶硅,其中该对导体中的至少一个导体由与非晶硅反应的金属硅化物制成,并且形成的硅化物区域是圆锥形。 另一种器件的特征在于,半导体层是非晶硅,其中该对导体中的至少一个导体由与非晶硅反应的金属硅化物形成,并且由此形成膜形成表面而不暴露 在氧化物气氛之间,形成无定形硅的步骤和形成金属的步骤。
    • 25. 发明授权
    • Data sorting circuit
    • 数据分类电路
    • US5822497A
    • 1998-10-13
    • US507467
    • 1995-09-29
    • Tadahiro OhmiTadashi ShibataTakeo Yamashita
    • Tadahiro OhmiTadashi ShibataTakeo Yamashita
    • G06F7/02G06F7/24G06G7/60G06N3/063G11C15/04H01L27/10H03K19/00H03K19/0948G06F15/18
    • G06F7/24G06N3/0635
    • A device comprising invertor circuit group including two or more invertor circuits formed by neuron MOS transistors; means for applying a first signal voltage common to the two or more invertors of the invertor circuit group to a first input gate of the invertor circuit; means for applying a given second signal to one or more second input gates other than the first input gate of the invertor circuits; a delay circuit for transmitting the variation of the output voltage of at least one of the invertor circuits of the invertor circuit group with a time delay generated by used of the variation with time of the signal voltage of either or both of the first and second signal voltages; a transistor whose ON and OFF is controlled by the signal transmitted from the delay circuit; storage circuits taking in signals by the ON and OFF of the transistor; and means for executing a given logical operation with respect to the output voltage signals generated by the invertor circuit group. The device has a function of storing the result of the logical operation in the storage circuit.
    • PCT No.PCT / JP94 / 00262 Sec。 371 1995年9月29日第 102(e)1995年9月29日PCT PCT 1994年2月22日PCT公布。 公开号WO94 / 19760 日期1994年9月1日包括由神经元MOS晶体管形成的包括两个或更多个反相器电路的逆变器电路组的器件; 用于将所述逆变器电路组的两个或更多个反相器公共的第一信号电压施加到所述逆变器电路的第一输入门的装置; 用于将给定的第二信号施加到除了逆变器电路的第一输入门之外的一个或多个第二输入门的装置; 延迟电路,用于通过使用随着第一和第二信号中的任一个或第二信号的信号电压的时间的变化而产生的时间延迟来发送反相器电路组的至少一个反相器电路的输出电压的变化 电压; 晶体管的ON和OFF由从延迟电路发送的信号控制; 存储电路通过晶体管的导通和截止来接收信号; 以及用于对由逆变器电路组产生的输出电压信号执行给定逻辑运算的装置。 该装置具有将逻辑运算的结果存储在存储电路中的功能。