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21. 发明授权

US08913444B1 Read operations and circuits for memory devices having programmable elements, including programmable resistance elements 有权
标题翻译：读取具有可编程元件的存储器件的操作和电路，包括可编程电阻元件
公开(公告)号：US08913444B1
公开(公告)日：2014-12-16
申请号：US13408797
申请日：2012-02-29
申请人： Nad Edward Gilbert , Ishai Naveh , Narbeh Derhacobian
发明人： Nad Edward Gilbert , Ishai Naveh , Narbeh Derhacobian
IPC分类号： G11C7/00
CPC分类号： G11C13/004 , G11C7/06 , G11C11/56 , G11C11/5614 , G11C13/0002 , G11C13/0011 , G11C16/26 , G11C2013/0054 , G11C2013/0057
摘要： A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.
摘要翻译：存储器件和方法可以使用多重检测操作来检测处于边缘状态的存储器元件的状态。在一些实施例中，评估电路可以响应于相同存储器元件的多个感测结果而产生用于存储器元件的输出值。在其他实施例中，存储器设备可以包括标准读取操作和强读操作，其中强读操作对于所选择的存储器元件比标准读操作应用更多的能量。

22. 发明授权

US08822967B2 Multi-terminal phase change devices 有权
标题翻译：多端相变装置
公开(公告)号：US08822967B2
公开(公告)日：2014-09-02
申请号：US13433039
申请日：2012-03-28
申请人： Louis Charles Kordus, II , Antonietta Oliva , Narbeh Derhacobian , Vei-Han Chan
发明人： Louis Charles Kordus, II , Antonietta Oliva , Narbeh Derhacobian , Vei-Han Chan
IPC分类号： H01L45/00 , H03K19/02 , G11C13/00
CPC分类号： H01L45/1226 , G11C13/0004 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/1683 , H03K19/02
摘要： Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.
摘要翻译：相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。结构允许应用，其中可以在两个活动终端之间产生电连接，并且使用单独的终端或终端来实现连接的控制。因此，可以独立于两个有源端子之间的路径的电阻增加加热器元件的电阻，允许使用较小的加热器元件，从而需要更少的电流以产生每单位面积相同量的焦耳加热。加热元件的电阻不影响相变装置的总电阻。编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

23. 发明授权

US06555436B2 Simultaneous formation of charge storage and bitline to wordline isolation 失效
公开(公告)号：US06555436B2
公开(公告)日：2003-04-29
申请号：US10223195
申请日：2002-08-19
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

24. 发明授权

US06501681B1 Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories 有权
标题翻译：在擦除验证期间使用低漏极偏置，以确保在声纳非易失性存储器中完全去除氮化物中的残留电荷
公开(公告)号：US06501681B1
公开(公告)日：2002-12-31
申请号：US09684694
申请日：2000-10-04
申请人： Michael Van Buskirk , Narbeh Derhacobian
发明人： Michael Van Buskirk , Narbeh Derhacobian
IPC分类号： G11C1606
CPC分类号： G11C16/344
摘要： An erase-verify operation is performed on a nonvolatile memory cell with an oxide-nitride-oxide structure by using a low drain bias voltage to allow residual charge remaining in the nitride layer after a typical erase operation to be detected effectively with a high degree of sensitivity.
摘要翻译：通过使用低漏极偏置电压，在具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元上进行擦除验证操作，以允许在典型的擦除操作之后残留在氮化物层中的剩余电荷以高度灵敏度。

25. 发明授权

US06307784B1 Negative gate erase 有权
标题翻译：负栅极擦除
公开(公告)号：US06307784B1
公开(公告)日：2001-10-23
申请号：US09795856
申请日：2001-02-28
申请人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
发明人： Darlene G. Hamilton , Narbeh Derhacobian , Kulachet Tanpairoj , Ravi Sunkavalli
IPC分类号： G11C1600
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/0475 , G11C16/3404 , G11C16/344 , G11C16/3445 , H01L27/115
摘要： A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.
摘要翻译：用于执行验证擦除的方法和系统包括对一个扇区中的每个I / O提供实质上高的电场的擦除脉冲。该操作对于单个电源设备是重要的，因为整个阵列的擦除频带到带电流的开始大于由排水泵提供的带电流。在第一个擦除脉冲之后，可以在所有IO上一起执行擦除验证程序。在一个特定示例中，选择Vdrain电压处于基本上高的正电压，并且Vgate电压的值处于基本上高的负电压，其中Vdrain和Vgate之间的电压电位也是基本上高的电压。

26. 发明授权

US06269023B1 Method of programming a non-volatile memory cell using a current limiter 有权
标题翻译：使用限流器对非易失性存储单元进行编程的方法
公开(公告)号：US06269023B1
公开(公告)日：2001-07-31
申请号：US09694729
申请日：2000-10-23
申请人： Narbeh Derhacobian , Janet S. Y. Wang , Daniel Sobek , Sameer S. Haddad
发明人： Narbeh Derhacobian , Janet S. Y. Wang , Daniel Sobek , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475
摘要： A memory cell that includes a substrate that has a first region and a second region with a channel therebetween, wherein the first region generates hot carriers. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge. A current limiter that limits the number of the generated hot carriers that can flow into the channel, wherein the current limiter does not control the voltage of the second region.
摘要翻译：一种存储单元，包括具有第一区域的基板和在其间具有通道的第二区域，其中所述第一区域产生热载流子。存储单元还包括通道上方的栅极和包含第一电荷量的电荷捕获区域。限流器，其限制可流入通道的所产生的热载体的数量，其中限流器不控制第二区域的电压。

27. 发明授权

US06246610B1 Symmetrical program and erase scheme to improve erase time degradation in NAND devices 有权
标题翻译：对称编程和擦除方案，以改善NAND器件中的擦除时间退化
公开(公告)号：US06246610B1
公开(公告)日：2001-06-12
申请号：US09511652
申请日：2000-02-22
申请人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
发明人： K. Michael Han , Joseph G. Pawletko , Narbeh Derhacobian , Chi Chang
IPC分类号： G11C1604
CPC分类号： G11C16/14 , G11C16/10 , G11C16/30
摘要： A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.
摘要翻译：一种编程和擦除方法，其通过使用恒定擦除电压和一组编程电压来延长非易失性存储器件的擦除时间劣化，其中编程电压组的平均编程电压近似等于恒定擦除电压。

28. 发明授权

US6159795A Low voltage junction and high voltage junction optimization for flash memory 失效
标题翻译：闪存的低电压结和高压结优化
公开(公告)号：US6159795A
公开(公告)日：2000-12-12
申请号：US109664
申请日：1998-07-02
申请人： Masaaki Higashitani , Hao Fang , Narbeh Derhacobian
发明人： Masaaki Higashitani , Hao Fang , Narbeh Derhacobian
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/976
摘要： An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.
摘要翻译：执行中间植入步骤以优化浮动型存储器集成电路的周边部分中的晶体管的性能。在相应的浮动栅型存储器件中形成浮置栅极的多晶硅层（Poly 1）防止优化注入穿透到形成浮栅存储器件的芯区域中。这允许在不需要附加掩模的情况下执行优化植入，从而降低成本和生产时间。

29. 发明授权

US6143608A Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation 有权
标题翻译：阻挡层在隧道氧化物氮化期间减少外围栅极区域的氮污染
公开(公告)号：US6143608A
公开(公告)日：2000-11-07
申请号：US283308
申请日：1999-03-31
申请人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
发明人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.
摘要翻译：本发明描述了在半导体芯片的周边区域中制造栅极氧化物区域的方法，其中栅极氧化物区域具有改善的电性能。所述方法包括在半导体芯片的周边上沉积阻挡层，以防止在半导体芯片的芯区域中的氮化步骤期间将杂质氮原子引入周围。通过防止周围的栅极区域的污染，如此产生的栅极氧化物区域具有增加的击穿电压和增加的可靠性。本发明描述了用于蚀刻用于保护周边免受隧道氧化物氮化的阻挡层的方法。用本发明的方法制造的半导体器件具有更长的预期寿命，并且可以以较高的器件密度制造。

30. 发明授权

US5844840A High voltage NMOS pass gate having supply range, area, and speed advantages 失效
标题翻译：具有供电范围，面积和速度优势的高压NMOS通道门
公开(公告)号：US5844840A
公开(公告)日：1998-12-01
申请号：US914543
申请日：1997-08-19
申请人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
发明人： Binh Quang Le , Pau-Ling Chen , Shane Charles Hollmer , Chung-You Hu , Narbeh Derhacobian
IPC分类号： G11C8/08 , G11C16/06
CPC分类号： G11C8/08
摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.
摘要翻译：根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压实际上驱动到字线上。根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。

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