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    • 6. 发明授权
    • Method of manufacturing high voltage transistor with modified field implant mask
    • 使用改进的场注入掩模制造高压晶体管的方法
    • US06514830B1
    • 2003-02-04
    • US10044510
    • 2002-01-11
    • Hao FangNarbeh Derhacobian
    • Hao FangNarbeh Derhacobian
    • H01L21336
    • H01L27/11526H01L27/11534
    • A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high gated diode breakdown voltage is provided in the manufacturing process by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.
    • 一种制造高栅极二极管击穿电压,低泄漏和低体效应的高压晶体管的方法,同时避免过多数量的昂贵的掩蔽步骤。 在制造过程中通过掩蔽来自常规场注入的高压结和从常规阈值调整植入物屏蔽源极/漏极区域来提供高栅极二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口,使得场离子注入距离结点不同的距离,从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸,从而产生具有低体效应的晶体管。
    • 7. 发明授权
    • High voltage transistor with modified field implant mask
    • 具有改进的场注入掩模的高压晶体管
    • US06351017B1
    • 2002-02-26
    • US09533057
    • 2000-03-22
    • Hao FangNarbeh Derhacobian
    • Hao FangNarbeh Derhacobian
    • H01L31119
    • H01L27/11526H01L27/11534
    • A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.
    • 形成具有高门控二极管击穿电压,低泄漏和低体效应的高电压晶体管,同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结以及从常规阈值调整植入物屏蔽源/漏区来提供高门控二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口,使得场离子注入距离结点不同的距离,从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸,从而产生具有低体效应的晶体管。
    • 8. 发明授权
    • Core field isolation for a NAND flash memory
    • NAND闪存的核心现场隔离
    • US06228782B1
    • 2001-05-08
    • US09309994
    • 1999-05-11
    • Hao FangMassaki HigashitaniNarbeh Derhacobian
    • Hao FangMassaki HigashitaniNarbeh Derhacobian
    • H01L21336
    • H01L27/11521H01L21/76216H01L27/115
    • Selective high-energy impurity implantation enables optimization of both core and peripheral field isolation without substantially degrading functionality, self-boosting efficiency or otherwise increasing program disturb, thereby improving device performance and reliability. Embodiments include high-energy impurity implantation, after forming core and peripheral field oxide regions in a semiconductor substrate, into the peripheral field oxide region and selected portions of the core field oxide regions corresponding to select transistor areas, while blocking the implant from the core memory cell channel regions. A channel stop implant is performed through the core field oxide regions after etching a first polysilicon layer. The high-energy impurity implant optimizes peripheral field isolation, without degrading self-boosting efficiency, because it is blocked from entering the memory cell channel region. The high-energy implant also enhances isolation in the select transistor areas, thereby preventing an increase in device malfunctions, while the channel stop implant optimizes core field isolation.
    • 选择性高能杂质注入使得能够优化核和外围场隔离,而不会显着降低功能性,自增强效率或以其他方式增加程序干扰,从而提高器件性能和可靠性。 实施例包括在半导体衬底中形成核心和外围场氧化物区域之后的高能杂质注入到对应于选择晶体管区域的外围场氧化物区域和核心场氧化物区域的选定部分,同时将核心存储器 细胞通道区。 在蚀刻第一多晶硅层之后,通过核心场氧化物区域进行沟道停止注入。 高能杂质注入优化外围场隔离,而不会降低自增强效率,因为它被阻止进入存储单元通道区。 高能量注入还增强了选择晶体管区域的隔离度,从而防止了器件故障的增加,而通道停止植入则优化了磁芯隔离。