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21. 发明授权

US07811944B2 Semiconductor device and a method of manufacture therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07811944B2
公开(公告)日：2010-10-12
申请号：US11167772
申请日：2005-06-27
申请人： Nace Rossi , Alvaro Maury
发明人： Nace Rossi , Alvaro Maury
IPC分类号： H01L21/31
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02131 , H01L21/02274 , H01L21/02362 , H01L21/31612 , H01L21/76801 , H01L21/76832 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括上述半导体器件的集成电路。根据本发明的原理，半导体器件可以包括衬底和位于衬底上的分级覆盖层，其中分级覆盖层包括至少两个不同的层，其中至少第二层和第二层两个不同的层具有不同的应力值。

22. 发明授权

US06309900B1 Test structures for testing planarization systems and methods for using same 有权
标题翻译：用于测试平面化系统的测试结构及其使用方法
公开(公告)号：US06309900B1
公开(公告)日：2001-10-30
申请号：US09480387
申请日：2000-01-11
申请人： Alvaro Maury , Frank Miceli , Subramanian Karthikeyan
发明人： Alvaro Maury , Frank Miceli , Subramanian Karthikeyan
IPC分类号： H01L2166
CPC分类号： H01L22/34
摘要： Test structures are disclosed for use in a system and with an associated method to test the effectiveness of planarization systems used in the fabrication of semiconductor devices and integrated circuits. A method of creating the test structure utilizes traditional semiconductor fabrication techniques, but uses substantially similar materials, such as oxide, for each of the layers of the test structure. Because the test structure comprises layers of substantially the same material, reliable uniform measurements of the thickness of the test structure may be obtained by an optical metrology tool. These measurements may then be analyzed and displayed in tabular reports or multi-dimensional plots to judge the effectiveness of the planarization system.
摘要翻译：公开了用于系统中的测试结构以及用于测试在半导体器件和集成电路的制造中使用的平面化系统的有效性的相关方法。创建测试结构的方法利用传统的半导体制造技术，但是对测试结构的每个层使用基本相似的材料，例如氧化物。由于测试结构包括基本上相同材料的层，所以通过光学测量工具可以获得测试结构的厚度的可靠的均匀测量。然后可以将这些测量结果分析并显示在表格报告或多维图中，以判断平面化系统的有效性。

23. 发明授权

US06261958B1 Method for performing chemical-mechanical polishing 有权
标题翻译：化学机械抛光方法
公开(公告)号：US06261958B1
公开(公告)日：2001-07-17
申请号：US09450485
申请日：1999-11-29
申请人： Annette Margaret Crevasse , Alvaro Maury , Sanjay Patel , John Thomas Sowell
发明人： Annette Margaret Crevasse , Alvaro Maury , Sanjay Patel , John Thomas Sowell
IPC分类号： H01L21302
CPC分类号： B24B37/11 , B24B45/00
摘要： An apparatus and method for performing chemical-mechanical polishing is disclosed in which the pad is secured to the platen without the use of adhesives. A polishing pad and a platen are secured together by a releasable attractive force; the force may comprise a vacuum or electromagnetic force, and the pad has a hard or magnetic backside layer for facing the plating and responding to the attractive force. This invention has particular application to chemical-mechanical polishing for use in planarizing dielectrics.
摘要翻译：公开了一种用于进行化学机械抛光的装置和方法，其中垫不用粘合剂固定在压板上。抛光垫和压板通过可释放的吸引力固定在一起; 力可以包括真空或电磁力，并且垫具有用于面对镀层并响应于吸引力的硬或磁性背面层。本发明特别适用于平面化电介质中使用的化学机械抛光。

24. 发明授权

US07005724B2 Semiconductor device and a method of manufacture therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07005724B2
公开(公告)日：2006-02-28
申请号：US10778454
申请日：2004-02-13
申请人： Nace Rossi , Alvaro Maury
发明人： Nace Rossi , Alvaro Maury
IPC分类号： H01L23/58
CPC分类号： H01L23/53295 , C23C16/401 , H01L21/02131 , H01L21/02274 , H01L21/02362 , H01L21/31612 , H01L21/76801 , H01L21/76832 , H01L21/823871 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the aforementioned semiconductor device. The semiconductor device, in accordance with the principles of the present invention, may include a substrate, and a graded capping layer located over the substrate, wherein the graded capping layer includes at least two different layers, wherein first and second layers of the at least two different layers have different stress values.
摘要翻译：本发明提供一种半导体器件及其制造方法以及包括上述半导体器件的集成电路。根据本发明的原理，半导体器件可以包括衬底和位于衬底上的分级覆盖层，其中分级覆盖层包括至少两个不同的层，其中至少第二层和第二层两个不同的层具有不同的应力值。

25. 发明授权

US06624039B1 Alignment mark having a protective oxide layer for use with shallow trench isolation 有权
标题翻译：对准标记具有用于浅沟槽隔离的保护性氧化物层
公开(公告)号：US06624039B1
公开(公告)日：2003-09-23
申请号：US09615122
申请日：2000-07-13
申请人： Mahjoub A. Abdelgadir , Stephen C. Kuehne , Alvaro Maury , Scott F. Shive
发明人： Mahjoub A. Abdelgadir , Stephen C. Kuehne , Alvaro Maury , Scott F. Shive
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device including large topography alignment marks, and a method of manufacture therefor. The method of manufacturing the semiconductor device includes forming an isolation trench and an alignment mark in a substrate to a substantially common depth, and forming an etch stop layer in the alignment mark.
摘要翻译：本发明提供一种包括大型地形对准标记的半导体器件及其制造方法。制造半导体器件的方法包括在衬底中形成隔离沟槽和对准标记至基本相同的深度，以及在对准标记中形成蚀刻停止层。

26. 发明授权

US06368972B1 Method for making an integrated circuit including alignment marks 有权
标题翻译：制造包括对准标记的集成电路的方法
公开(公告)号：US06368972B1
公开(公告)日：2002-04-09
申请号：US09345039
申请日：1999-06-30
申请人： Alvaro Maury , Scott Francis Shive
发明人： Alvaro Maury , Scott Francis Shive
IPC分类号： H01L21302
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for making an integrated circuit preferably includes the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region and to define a recess within the dielectric layer filling the trench to serve as an alignment mark; and polishing the selectively etched dielectric layer and leaving the alignment mark. The method may also include forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step. The alignment mark can be made with a step height which is greater than a conventional alignment mark formed by the step height difference between the active area and the dielectric layer of the trench. Accordingly, variations in polishing, for example, will not obscure or remove the alignment mark made in accordance with the present invention.
摘要翻译：制造集成电路的方法优选包括以下步骤：在半导体衬底中横向邻近有源区形成沟槽; 在所述半导体衬底上形成填充所述沟槽并覆盖所述有源区的介电层; 选择性地蚀刻介电层以去除覆盖有源区的电介质层的至少一部分，并且在填充沟槽的电介质层内限定用作对准标记的凹槽; 并抛光选择性蚀刻的介电层并留下对准标记。该方法还可以包括在抛光的介电层附近形成光学不透明层，并且与对准标记形成在光学不透明层中重复的对准标记。对准标记和/或重复的对准标记可用于在随后的处理步骤中进行对准。对准标记可以以比由沟槽的有源区和电介质层之间的台阶高度差形成的常规对准标记更大的台阶高度制成。因此，抛光的变化例如不会使根据本发明制造的对准标记模糊或去除。

27. 发明授权

US06217419B1 Chemical-mechanical polisher 失效
标题翻译：化学机械抛光机
公开(公告)号：US06217419B1
公开(公告)日：2001-04-17
申请号：US09375085
申请日：1999-08-16
申请人： Alvaro Maury , Jose Rodriguez
发明人： Alvaro Maury , Jose Rodriguez
IPC分类号： B24B100
CPC分类号： B24B37/11 , B24B49/16
摘要： A chemical-mechanical polishing apparatus includes a polishing table having a top surface and an annular trench formed in the top surface and defining an annular configured polishing area in the polishing table. A drive mechanism rotates the polishing table. An annular diaphragm is positioned within the annular configured polishing area and has a top surface and bottom surface. An annular configured polishing pad is positioned on the diaphragm. A fluid actuated pressure mechanism is associated with the annular configured polishing area for exerting pressure upward onto the bottom surface of the annular diaphragm as a polishing table rotates for exerting an upward biasing pressure onto the polishing pad and imparting a desired counter force against any downward pressure exerted against a semiconductor wafer during chemical-mechanical polishing.
摘要翻译：化学机械抛光装置包括具有顶表面和形成在顶表面中的环形沟槽并且在抛光台中限定环形构造的抛光区域的抛光台。驱动机构使抛光台旋转。环形隔膜位于环形构造的抛光区域内，并具有顶表面和底表面。环形构造的抛光垫定位在隔膜上。流体致动的压力机构与环形构造的抛光区域相关联，用于在抛光台旋转时将压力向上施加到环形隔膜的底表面上，以向上施加向上的偏置压力到抛光垫上，并且对任何向下的压力施加所需的反作用力在化学机械抛光期间对半导体晶片施加。

28. 发明授权

US6146975A Shallow trench isolation 失效
标题翻译：浅沟隔离
公开(公告)号：US6146975A
公开(公告)日：2000-11-14
申请号：US113583
申请日：1998-07-10
申请人： Stephen Carl Kuehne , Alvaro Maury
发明人： Stephen Carl Kuehne , Alvaro Maury
IPC分类号： H01L21/762 , H01L21/76 , H01L29/00
CPC分类号： H01L21/76229
摘要： The specification describes a dual patterned polish stop layer technique for shallow trench isolation. The shallow trenches are formed by etching trenches in a semiconductor substrate wafer, backfilling with oxide, and polishing by chemical-mechanical polishing (CMP) to produce a planar, trench isolated, wafer. To ensure planarity of the wafer after CMP, and avoid dishing of the field oxide, a dual silicon nitride polish stop layer is used. The first polish stop layer is applied selectively to protect the active device regions, and the second polish stop layer is applied selectively to protect the field oxide regions.
摘要翻译：该说明书描述了用于浅沟槽隔离的双重图案化抛光停止层技术。浅沟槽通过蚀刻半导体衬底晶片中的沟槽，用氧化物回填和通过化学机械抛光（CMP）进行抛光来形成，以产生平面的，沟槽隔离的晶片。为了确保CMP之后的晶片的平面度，并且避免场氧化物的凹陷，则使用双重氮化硅抛光停止层。选择性地施加第一抛光停止层以保护有源器件区域，并且选择性地施加第二抛光停止层以保护场氧化物区域。

29. 发明授权

US6051500A Device and method for polishing a semiconductor substrate 失效
标题翻译：用于研磨半导体衬底的装置和方法
公开(公告)号：US6051500A
公开(公告)日：2000-04-18
申请号：US80992
申请日：1998-05-19
申请人： Alvaro Maury , Arun K. Nanda , Omar Rodriguez
发明人： Alvaro Maury , Arun K. Nanda , Omar Rodriguez
IPC分类号： B24B1/04 , B24B37/04 , H01L21/304 , H01L21/321 , H01L21/768
CPC分类号： B24B1/04 , B24B37/042 , H01L21/3212 , H01L21/7684
摘要： The present invention provides a method for polishing a semiconductor substrate having a first layer of material formed on a second layer of different material. In one embodiment, the method includes placing the semiconductor substrate against a polishing surface and polishing the semiconductor substrate, producing a first vibration by polishing and removing the first layer, producing a second vibration by polishing at least a portion of the second layer, and detecting a change from the first vibration to the second vibration with a vibration sensor. The vibration that is sensed in the present invention is physical or mechanical vibration, and it is not a vibration associated with a change in temperature. The vibration sensor may be of varying types. For example, the vibration sensor may be an acoustic sensor or an ultrasonic sensor.
摘要翻译：本发明提供一种用于研磨具有形成在不同材料的第二层上的第一材料层的半导体衬底的方法。在一个实施例中，该方法包括将半导体衬底放置在抛光表面上并抛光半导体衬底，通过抛光和去除第一层产生第一振动，通过抛光第二层的至少一部分产生第二振动，以及检测用振动传感器从第一次振动到第二次振动的变化。在本发明中感测到的振动是物理或机械振动，并且它不是与温度变化相关联的振动。振动传感器可以是不同类型的。例如，振动传感器可以是声传感器或超声波传感器。

30. 发明授权

US6008123A Method for using a hardmask to form an opening in a semiconductor substrate 失效
标题翻译：使用硬掩模在半导体衬底中形成开口的方法
公开(公告)号：US6008123A
公开(公告)日：1999-12-28
申请号：US963687
申请日：1997-11-04
申请人： Taeho Kook , Alvaro Maury , Kurt G. Steiner , Tungsheng Yang
发明人： Taeho Kook , Alvaro Maury , Kurt G. Steiner , Tungsheng Yang
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/768 , H01L29/78 , H01L21/8242
CPC分类号： H01L21/31144 , H01L21/76816 , Y10S438/947
摘要： The present invention provides a method of forming a opening in a semiconductor dielectric layer. In an advantageous embodiment, the method comprises the steps of forming a hardmask layer on the dielectric layer wherein the hardmask layer has an etch rate less than an etch rate of the dielectric layer, forming a guide opening through the hardmask layer, forming a spacer within the guide opening that reduces a diameter of the guide opening and forming the opening in the dielectric layer through the guide opening. The method may further include the steps of depositing a conductive material in the opening and guide opening and over at least a portion of the hardmask layer that extends beyond the guide opening, and removing the hardmask layer and the conductive material layer that extend beyond the guide opening. In certain embodiments, the contact opening may be formed to a width equal to or less than 0.25 .mu.m.
摘要翻译：本发明提供一种在半导体电介质层中形成开口的方法。在有利的实施例中，该方法包括以下步骤：在电介质层上形成硬掩模层，其中硬掩模层的蚀刻速率小于电介质层的蚀刻速率，形成通过硬掩模层的引导开口，所述引导开口减小所述引导开口的直径并且通过所述引导开口在所述介电层中形成所述开口。该方法可以进一步包括以下步骤：将导电材料沉积在开口和引导开口中以及在延伸超过引导开口的硬掩模层的至少一部分之上，以及移除延伸超过引导件的硬掩模层和导电材料层开放在某些实施例中，接触开口可以形成为等于或小于0.25μm的宽度。

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