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21. 发明授权

US07768430B1 Look-up table based memory 有权
标题翻译：基于查询表的内存
公开(公告)号：US07768430B1
公开(公告)日：2010-08-03
申请号：US12124091
申请日：2008-05-20
申请人： Philip Pan , Andy L. Lee
发明人： Philip Pan , Andy L. Lee
IPC分类号： H03M7/00
CPC分类号： H03K19/1776 , G11C8/10 , G11C8/16 , H03K19/17728
摘要： An integrated circuit (IC) having selectable memory elements is provided. The IC includes a logic array block (LAB) disposed within the IC. A plurality of logic elements, having look-up tables functioning as the selectable memory elements is included in the LAB. Within a logic element, a data path that shares multiplexers and drivers when the look-up tables of the logic elements are operated as one of a memory element or a combinational logic device is provided. In addition, a write address decoder is interconnected with the plurality of logic elements through a write bus.
摘要翻译：提供具有可选存储元件的集成电路（IC）。 IC包括设置在IC内的逻辑阵列块（LAB）。具有用作可选存储元件的查找表的多个逻辑元件包括在LAB中。在逻辑元件中，提供了当逻辑元件的查找表作为存储元件或组合逻辑器件之一来操作时共享复用器和驱动器的数据路径。此外，写地址解码器通过写总线与多个逻辑元件互连。

22. 发明申请

US20090224800A1 PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS 有权
标题翻译：用于柔性布置IP功能块的PLD架构
公开(公告)号：US20090224800A1
公开(公告)日：2009-09-10
申请号：US12465464
申请日：2009-05-13
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

23. 发明授权

US07405589B2 Apparatus and methods for power management in integrated circuits 有权
标题翻译：集成电路中电源管理的装置和方法
公开(公告)号：US07405589B2
公开(公告)日：2008-07-29
申请号：US11316390
申请日：2005-12-22
申请人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
发明人： David Lewis , Christopher F. Lane , Sarathy Sribhashyam , Srinivas Perisetty , Tim Vanderhoek , Vaughn Betz , Thomas Yau-Tsun Wong , Andy L. Lee
IPC分类号： H03K19/173
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.
摘要翻译：可编程逻辑器件（PLD）包括非易失性存储器，配置存储器和控制电路。控制电路耦合到非易失性存储器和配置存储器。一组电压从控制电路的输出导出，并被应用于PLD内的电路。

24. 发明授权

US07058920B2 Methods for designing PLD architectures for flexible placement of IP function blocks 失效
标题翻译：设计用于灵活放置IP功能块的PLD架构的方法
公开(公告)号：US07058920B2
公开(公告)日：2006-06-06
申请号：US10460685
申请日：2003-06-11
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
摘要翻译：根据本发明的一个方面，通过中断LE阵列基本信号路由体系结构，在PLD的LE阵列内形成一个孔，使得留下用于IP功能块的孔。提供接口区域用于将剩余的LE阵列基本信号路由体系结构与IP功能块进行接口。

25. 发明授权

US06937064B1 Versatile logic element and logic array block 有权
公开(公告)号：US06937064B1
公开(公告)日：2005-08-30
申请号：US10280723
申请日：2002-10-24
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

26. 发明授权

US06879183B2 Programmable logic device architectures with super-regions having logic regions and a memory region 有权
标题翻译：具有逻辑区域和存储区域的超区域的可编程逻辑器件架构
公开(公告)号：US06879183B2
公开(公告)日：2005-04-12
申请号：US10260712
申请日：2002-09-27
申请人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
发明人： David E. Jefferson , Cameron McClintock , James Schleicher , Andy L. Lee , Manuel Mejia , Bruce B. Pedersen , Christopher F. Lane , Richard G. Cliff , Srinivas T. Reddy
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A programmable logic device has a plurality of super-regions of programmable circuitry disposed on the device in a two-dimensional array of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of programmable memory. Each logic region includes a plurality of subregions of programmable logic. Each super-region has associated interconnection resources for allowing communication between the logic and memory regions of that super-region without the need to use, for such relatively local interconnections, the longer-length inter-super-region interconnection resources that are also provided on the device.
摘要翻译：可编程逻辑器件具有设置在这种超区域的二维阵列中的设备上的多个可编程电路的超区域。每个超区域包括可编程逻辑的多个区域和可编程存储器的区域。每个逻辑区域包括可编程逻辑的多个子区域。每个超区域具有相关联的互连资源，用于允许该超区域的逻辑和存储器区域之间的通信，而不需要为这样的相对局部互连使用也提供在较高长度的超超区域互连资源装置。

27. 发明授权

US06859065B2 Use of dangling partial lines for interfacing in a PLD 失效
标题翻译：使用悬挂的部分线路在PLD中进行接口
公开(公告)号：US06859065B2
公开(公告)日：2005-02-22
申请号：US10650465
申请日：2003-08-27
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Giles V. Powell , Paul Leventis
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17748 , H03K19/17732 , H03K19/17736
摘要： A routing structure in a PLD is implemented in a staggered fashion. Routing lines that would otherwise be “partial” and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.
摘要翻译： PLD中的路由结构以交错方式实现。否则将在路由架构边界“部分”和悬挂的路由线被驱动，为从边界向PLD核心路由信号提供了额外的灵活性。

28. 发明授权

US06826741B1 Flexible I/O routing resources 有权
标题翻译：灵活的I / O路由资源
公开(公告)号：US06826741B1
公开(公告)日：2004-11-30
申请号：US10289629
申请日：2002-11-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
摘要翻译：在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由，可能包括I / O到核心，核到I / O和核心到核心的路由。在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

29. 发明授权

US06605962B2 PLD architecture for flexible placement of IP function blocks 有权
公开(公告)号：US06605962B2
公开(公告)日：2003-08-12
申请号：US10057442
申请日：2002-01-25
申请人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
发明人： Andy L. Lee , Cameron McClintock , Brian Johnson , Richard Cliff , Srinivas Reddy , Chris Lane , Paul Leventis , Vaughn Timothy Betz , David Lewis
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/177 , H03K19/17732 , H03K19/1778 , H03K19/17796
摘要： In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

30. 发明授权

US06563367B1 Interconnection switch structures 有权
标题翻译：互连开关结构
公开(公告)号：US06563367B1
公开(公告)日：2003-05-13
申请号：US09930863
申请日：2001-08-16
申请人： Andy L. Lee
发明人： Andy L. Lee
IPC分类号： H03K1716
CPC分类号： H03K17/063
摘要： An improved interconnection switch using NMOS passgates is presented which allows the gate voltage of the NMOS passgate to be bootstrapped to a higher voltage than the initial voltage applied thereon so as to allow a higher logic HIGH signal to be passed. The stimulus for this bootstrapping is the transition of the logic signal at the input terminal of the NMOS passgate, which obviates the need for a separate external stimulus. Because the bootstrapping occurs as a result of the dynamic coupling between the gate terminal and the channel of the NMOS passgate, the voltage across the gate oxide does not exceed the magnitude of the logic HIGH signal, thereby rendering the use of thick-oxide devices unnecessary.
摘要翻译：提出了一种使用NMOS通道的改进的互连开关，其允许NMOS通道的栅极电压被引导到比施加在其上的初始电压更高的电压，以便允许更高的逻辑高电平信号通过。这种自举的刺激是NMOS通道输入端的逻辑信号的转变，这消除了对单独的外部刺激的需要。由于由于门极和NMOS通道的通道之间的动态耦合而引起自举，栅极氧化物两端的电压不会超过逻辑高电平信号的大小，从而使得不需要使用厚氧化物器件。

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