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21. 发明授权

US07741663B2 Air gap spacer formation 有权
标题翻译：气隙间隔物形成
公开(公告)号：US07741663B2
公开(公告)日：2010-06-22
申请号：US12258188
申请日：2008-10-24
申请人： Fred Hause , Anthony C. Mowry , David G. Farber , Markus E. Lenski
发明人： Fred Hause , Anthony C. Mowry , David G. Farber , Markus E. Lenski
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/41775 , H01L29/6653 , H01L29/6656 , H01L29/7833 , Y10S257/90
摘要： Miniaturized complex transistor devices are formed with reduced leakage and reduced miller capacitance. Embodiments include transistors having reduced capacitance between the gate electrode and source/drain contact, as by utilizing a low-K dielectric constant sidewall spacer material. An embodiment includes forming a gate electrode on a semiconductor substrate, forming a sidewall spacer on the side surfaces of the gate electrode, forming source/drain regions by ion implantation, forming an interlayer dielectric over the gate electrode, sidewall spacers, and substrate, and forming a source/drain contact through the interlayer dielectric. The sidewall spacers and interlayer dielectric are then removed. A dielectric material, such as a low-K dielectric material, is then deposited in the gap between the gate electrode and the source/drain contact so that an air gap is formed, thereby reducing the parasitic “miller” capacitance.
摘要翻译：小型化的复合晶体管器件形成有减少的泄漏和减小的磨机电容。实施例包括通过利用低K介电常数侧壁间隔物材料在栅电极和源极/漏极接触之间具有减小的电容的晶体管。一个实施例包括在半导体衬底上形成栅电极，在栅电极的侧表面上形成侧壁间隔物，通过离子注入形成源/漏区，在栅电极，侧壁间隔物和衬底上形成层间电介质，以及通过层间电介质形成源极/漏极接触。然后去除侧壁间隔物和层间电介质。然后将诸如低K电介质材料的电介质材料沉积在栅电极和源极/漏极接触之间的间隙中，从而形成气隙，由此减小寄生“铣”电容。

22. 发明授权

US07670932B2 MOS structures with contact projections for lower contact resistance and methods for fabricating the same 有权
标题翻译：具有用于较低接触电阻的接触突起的MOS结构及其制造方法
公开(公告)号：US07670932B2
公开(公告)日：2010-03-02
申请号：US11762133
申请日：2007-06-13
申请人： Jianhong Zhu , Fred Hause , David Wu
发明人： Jianhong Zhu , Fred Hause , David Wu
IPC分类号： C12N15/75
CPC分类号： H01L21/28518 , H01L21/28247 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： MOS structures with contact projections for lower contact resistance and methods for fabricating such MOS structures have been provided. In an embodiment, a method comprises providing a semiconductor substrate, fabricating a gate stack on the substrate, and forming a contact projection on the substrate. Ions of a conductivity-determining type are implanted within the substrate using the gate stack as an ion implantation mask to form impurity-doped regions within the substrate. A metal silicide layer is formed on the contact projection and a contact is formed to the metal silicide layer. The contact is in electrical communication with the impurity-doped regions via the contact projection.
摘要翻译：已经提供了具有用于较低接触电阻的接触突起的MOS结构以及用于制造这种MOS结构的方法。在一个实施例中，一种方法包括提供半导体衬底，在衬底上制造栅极堆叠，以及在衬底上形成接触突起。使用栅极堆叠作为离子注入掩模将电导率确定类型的离子注入到衬底内，以在衬底内形成杂质掺杂区域。在接触突起上形成金属硅化物层，并且与金属硅化物层形成接触。触点通过接触突起与杂质掺杂区电连通。

23. 发明授权

US06873051B1 Nickel silicide with reduced interface roughness 有权
标题翻译：硅化硅，界面粗糙度降低
公开(公告)号：US06873051B1
公开(公告)日：2005-03-29
申请号：US10157807
申请日：2002-05-31
申请人： Eric Paton , Paul Raymond Besser , Simon S. Chan , Fred Hause
发明人： Eric Paton , Paul Raymond Besser , Simon S. Chan , Fred Hause
IPC分类号： H01L21/28 , H01L21/00 , H01L21/265 , H01L21/285 , H01L21/336 , H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28052 , H01L29/665 , H01L29/6659
摘要： Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.
摘要翻译：通过在下面的硅和硅化镍层之间形成扩散转换层来实现具有显着降低的界面粗糙度的硅化镍形成。实施例包括将氮离子注入到衬底和栅电极中，沉积钛或钽的薄层，沉积镍层，然后加热以形成在下硅和硅化镍层之间的界面处含有氮的扩散调制层。

24. 发明授权

US6159814A Spacer formation by poly stack dopant profile design 失效
标题翻译：通过多层掺杂剂分布设计形成间隔物
公开(公告)号：US6159814A
公开(公告)日：2000-12-12
申请号：US968444
申请日：1997-11-12
申请人： Mark Gardner , Fred Hause , Charles May
发明人： Mark Gardner , Fred Hause , Charles May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L21/28211 , H01L21/28052 , H01L21/28176 , H01L29/6659 , H01L29/7833
摘要： A method for forming a semiconductor device to produce graded doping in the source region and the drain region includes the steps of implanting the gate material, usually a polysilicon, with a dopant ion that varies the level of oxide formation on the gate. The dopant ion is driven into undoped polysilicon. Nitrogen ions, may also be implanted in the polysilicon to contain the previously implanted ions. For N-type transistors, typically arsenic is implanted. For P-type transistors, typically boron is implanted. Gates are formed. The gate structure is then oxidized. The oxidation process is controlled to grow a desired thickness of silicon dioxide on the gate. The portion of the gate carrying the dopant grows silicon dioxide either more quickly or more slowly. An isotropic etch can then used to remove a portion of the silicon oxide and form a knob on each sidewall of the gate. A heavy ion implant is then done to convert a portion of the lightly doped source region into a heavily doped region within the source region, and to convert a portion of the lightly doped drain region into a heavily doped region within the drain region. Some of the implanted ions are stopped by the knobs on the gate sidewalls. The regions under the knobs do not have as deep an ion implantation resulting in a shallow region beneath the knob. This forms a graded junction having a specific geometry. The geometry of the interface between the lightly doped region and the heavily doped region in the source region and the drain region depends on the geometry (thickness) of silicon dioxide knobs formed on the sidewall of the gate.
摘要翻译：用于形成在源极区域和漏极区域中产生渐变掺杂的半导体器件的方法包括以下步骤：通过改变栅极上的氧化物形成水平的掺杂剂离子注入栅极材料（通常为多晶硅）。掺杂剂离子被驱入未掺杂的多晶硅。氮离子也可以注入到多晶硅中以容纳先前注入的离子。对于N型晶体管，通常植入砷。对于P型晶体管，通常植入硼。门形成。然后将栅极结构氧化。控制氧化过程以在栅极上生长所需的二氧化硅厚度。携带掺杂剂的栅极部分会更快或更慢地生长二氧化硅。然后可以使用各向同性蚀刻去除氧化硅的一部分并在栅极的每个侧壁上形成旋钮。然后进行重离子注入以将轻掺杂源区的一部分转换为源区内的重掺杂区，并将轻掺杂漏区的一部分转换为漏区内的重掺杂区。一些注入的离子被栅极侧壁上的旋钮阻挡。旋钮下面的区域没有深度的离子注入，导致旋钮下方的浅区域。这形成具有特定几何形状的渐变连接点。源极区域和漏极区域中的轻掺杂区域和重掺杂区域之间的界面的几何形状取决于形成在栅极侧壁上的二氧化硅旋钮的几何形状（厚度）。

25. 发明授权

US6027859A Semiconductor substrate having extended scribe line test structure and method of fabrication thereof 失效
标题翻译：具有延长的划片线测试结构的半导体衬底及其制造方法
公开(公告)号：US6027859A
公开(公告)日：2000-02-22
申请号：US992234
申请日：1997-12-17
申请人： Robert Dawson , Mark W. Michael , Fred Hause
发明人： Robert Dawson , Mark W. Michael , Fred Hause
IPC分类号： G03F7/20
CPC分类号： G03F7/70633 , G03F7/70475
摘要： The present invention generally provides a semiconductor substrate having an extended test structure and a method of fabricating such a substrate. A method of forming an extended test structure on a semiconductor substrate, consistent with one embodiment of the invention, includes forming a first test structure pattern over a first portion of the substrate and forming a second test structure pattern of the second portion of the substrate which partially overlaps the first portion of the substrate such that the first test structure pattern and the second test structure overlap. The first test structure pattern may be formed using, for example, reticle and a second test structure pattern may be formed using the same reticle. The first and second test structure patterns may, for example, be formed in a scribe line of the substrate.
摘要翻译：本发明通常提供具有扩展测试结构的半导体衬底和制造这种衬底的方法。根据本发明的一个实施例，在半导体衬底上形成扩展测试结构的方法包括在衬底的第一部分上形成第一测试结构图案，并形成衬底的第二部分的第二测试结构图案，部分地与衬底的第一部分重叠，使得第一测试结构图案和第二测试结构重叠。可以使用例如掩模版形成第一测试结构图案，并且可以使用相同的掩模版形成第二测试结构图案。第一和第二测试结构图案可以例如形成在基板的划线中。

26. 发明授权

US08564120B2 Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside 有权
标题翻译：半导体器件的温度关键器件区域的散热通过连接到衬底背面的热管进行散热
公开(公告)号：US08564120B2
公开(公告)日：2013-10-22
申请号：US12642989
申请日：2009-12-21
申请人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
发明人： Anthony Mowry , David Farber , Fred Hause , Markus Lenski
IPC分类号： H01L23/36 , H01L21/00
CPC分类号： H01L23/427 , H01L23/3677 , H01L23/481 , H01L23/522 , H01L27/16 , H01L2224/16 , H01L2224/73253 , H01L2924/01019 , H01L2924/13091 , H01L2924/15311 , H01L2924/3025 , H01L2924/00
摘要： By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.
摘要翻译：通过在半导体器件的温度关键区域中提供散热元件或热管，可以实现增强的性能，可靠性和封装密度。散热元件可以基于标准制造技术形成，并且可以定位成紧靠各个晶体管元件和/或可用于屏蔽特定的电路部分。

27. 发明授权

US07804107B1 Thyristor semiconductor device and method of manufacture 失效
标题翻译：晶闸管半导体器件及其制造方法
公开(公告)号：US07804107B1
公开(公告)日：2010-09-28
申请号：US11906619
申请日：2007-10-03
申请人： Andrew E. Horch , Fred Hause
发明人： Andrew E. Horch , Fred Hause
IPC分类号： H01L31/111
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/823835 , H01L27/1027 , H01L27/1203 , H01L29/66378
摘要： In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask. Epitaxial material may then be formed selectively over exposed regions of the semiconductor material as defined by the silicide-blocking mask. Silicide might also be formed after select exposed regions as defined by the silicide-blocking mask. The silicide-blocking mask may thus be used for alignment of implants, and also for defining epitaxial and silicide alignments.
摘要翻译：在半导体器件的处理方法中，可以在半导体材料上形成硅化物阻挡层。在限定硅化物阻挡层之后，可以将杂质注入半导体材料的部分，如由硅化物阻挡层所限定的。在植入之后，硅化物可以形成在半导体材料的表面区域，如硅化物阻挡层所允许的。杂质植入物的区域可以包括与其上形成的硅化物的轮廓相关的边界。在另一实施例中，植入物可以限定到晶闸管器件的基极区域。可以以入射角来执行植入物，以将阻挡掩模的外围边缘下方的基底区域的部分延伸。接下来，可以使用基本上正交的入射角并与掩模自对准的植入物形成阳极 - 发射极区域。然后可以在由硅化物阻挡掩模限定的半导体材料的暴露区域上选择性地形成外延材料。也可以在由硅化物阻挡掩模定义的选择的暴露区域之后形成硅化物。硅化物阻挡掩模因此可用于植入物的对准，并且还用于限定外延和硅化物对准。

28. 发明授权

US07745337B2 Method of optimizing sidewall spacer size for silicide proximity with in-situ clean 有权
标题翻译：用于原位清洁优化硅化物接近的侧壁间隔尺寸的方法
公开(公告)号：US07745337B2
公开(公告)日：2010-06-29
申请号：US12122840
申请日：2008-05-19
申请人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
发明人： David G. Farber , Fred Hause , Markus Lenski , Anthony C. Mowry
IPC分类号： H01L21/311
CPC分类号： H01L29/665 , H01L21/28052 , H01L29/6653 , H01L29/78
摘要： A method that includes forming a gate of a semiconductor device on a substrate, and etching sidewall spacers on sides of the gate to provide a proximity value, where the proximity value is defined as a distance between the gate and an edge of a performance-enhancing region. The sidewall spacers are used to define the edge of the region during formation of the region in the substrate. The method also includes pre-cleaning the gate and the substrate in preparation for formation of the region, where the etching and the pre-cleaning are performed in a continuous vacuum.
摘要翻译：一种方法，包括在衬底上形成半导体器件的栅极，并且蚀刻栅极侧面上的侧壁间隔物以提供接近值，其中接近值被定义为栅极与性能增强的边缘之间的距离地区。侧壁间隔件用于在衬底中形成区域期间限定区域的边缘。该方法还包括预先清洁栅极和基板以准备形成区域，其中在连续真空中进行蚀刻和预清洁。

29. 发明授权

US06967160B1 Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness 有权
标题翻译：制造具有降低界面粗糙度的硅化镍的半导体器件的方法
公开(公告)号：US06967160B1
公开(公告)日：2005-11-22
申请号：US11042194
申请日：2005-01-26
申请人： Eric Paton , Paul Raymond Besser , Simon S. Chan , Fred Hause
发明人： Eric Paton , Paul Raymond Besser , Simon S. Chan , Fred Hause
IPC分类号： H01L21/28 , H01L21/00 , H01L21/265 , H01L21/285 , H01L21/336 , H01L21/44 , H01L23/48 , H01L23/52 , H01L29/40 , H01L29/78 , H01L29/786
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28052 , H01L29/665 , H01L29/6659
摘要： Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.
摘要翻译：通过在下面的硅和硅化镍层之间形成扩散转换层来实现具有显着降低的界面粗糙度的硅化镍形成。实施例包括将氮离子注入到衬底和栅电极中，沉积钛或钽的薄层，沉积镍层，然后加热以形成在下硅和硅化镍层之间的界面处含有氮的扩散调制层。

30. 发明申请

US20050101120A1 Method of forming local interconnect barrier layers 审中-公开
标题翻译：形成局部互连阻挡层的方法
公开(公告)号：US20050101120A1
公开(公告)日：2005-05-12
申请号：US10400212
申请日：2003-03-27
申请人： Fred Hause , Gert Burbach , Volker Kahlert
发明人： Fred Hause , Gert Burbach , Volker Kahlert
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76856
摘要： In a barrier formation process, an adhesion layer of refractory metal is deposited on sidewalls and bottom portions of a trench, and, subsequently, a nitride layer of the refractory metal is formed on the adhesion layer. After forming the nitride layer, the substrate is subjected to a heat treatment in a nitrogen-containing atmosphere to further convert residual refractory metal into nitride, thereby improving the barrier properties of the nitride layer in a subsequent process for filling in a contact metal, such as tungsten.
摘要翻译：在阻挡层形成工艺中，将难熔金属的粘合层沉积在沟槽的侧壁和底部上，随后在粘合层上形成难熔金属的氮化物层。在形成氮化物层之后，将基板在含氮气氛中进行热处理，以将残余难熔金属进一步转化为氮化物，从而在随后的填充接触金属的过程中改善氮化物层的阻挡性能，作为钨。

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