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1. 发明授权

US6027859A Semiconductor substrate having extended scribe line test structure and method of fabrication thereof 失效
标题翻译：具有延长的划片线测试结构的半导体衬底及其制造方法
公开(公告)号：US6027859A
公开(公告)日：2000-02-22
申请号：US992234
申请日：1997-12-17
申请人： Robert Dawson , Mark W. Michael , Fred Hause
发明人： Robert Dawson , Mark W. Michael , Fred Hause
IPC分类号： G03F7/20
CPC分类号： G03F7/70633 , G03F7/70475
摘要： The present invention generally provides a semiconductor substrate having an extended test structure and a method of fabricating such a substrate. A method of forming an extended test structure on a semiconductor substrate, consistent with one embodiment of the invention, includes forming a first test structure pattern over a first portion of the substrate and forming a second test structure pattern of the second portion of the substrate which partially overlaps the first portion of the substrate such that the first test structure pattern and the second test structure overlap. The first test structure pattern may be formed using, for example, reticle and a second test structure pattern may be formed using the same reticle. The first and second test structure patterns may, for example, be formed in a scribe line of the substrate.
摘要翻译：本发明通常提供具有扩展测试结构的半导体衬底和制造这种衬底的方法。根据本发明的一个实施例，在半导体衬底上形成扩展测试结构的方法包括在衬底的第一部分上形成第一测试结构图案，并形成衬底的第二部分的第二测试结构图案，部分地与衬底的第一部分重叠，使得第一测试结构图案和第二测试结构重叠。可以使用例如掩模版形成第一测试结构图案，并且可以使用相同的掩模版形成第二测试结构图案。第一和第二测试结构图案可以例如形成在基板的划线中。

2. 发明授权

US06552776B1 Photolithographic system including light filter that compensates for lens error 有权
标题翻译：光刻系统包括补偿透镜误差的滤光片
公开(公告)号：US06552776B1
公开(公告)日：2003-04-22
申请号：US09183176
申请日：1998-10-30
申请人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
发明人： Derick J. Wristers , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Bradley T. Moore , Mark W. Michael
IPC分类号： G03B2754
CPC分类号： G03F7/70558 , G03F7/70191 , G03F7/706
摘要： A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
摘要翻译：公开了一种光刻系统，其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。以这种方式，当透镜错误导致导致图像图案的放大部分的聚焦变化时，光过滤器降低传输到图像图案的扩大部分的光强度。这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。结果，在光致抗蚀剂层显影之后，由于滤光器而导致透镜误差导致的线宽变化会降低。优选地，光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜，并且光吸收膜的厚度根据测量的尺寸而变化数据以提供所需的光强度变化。本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。

3. 发明授权

US06323095B1 Method for reducing junction capacitance using a halo implant photomask 有权
标题翻译：使用光晕植入光掩模降低结电容的方法
公开(公告)号：US06323095B1
公开(公告)日：2001-11-27
申请号：US09489178
申请日：2000-01-21
申请人： Mark W. Michael , Jon D. Cheek , Robert Dawson
发明人： Mark W. Michael , Jon D. Cheek , Robert Dawson
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L21/266 , H01L21/8238 , H01L29/1083
摘要： A method for forming a semiconductor device is provided. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped region extends a first distance from the gate. A second doped region is formed in the substrate. The second doped region extends a second distance from the gate. The first distance is less than the second distance. A semiconductor device includes a substrate, isolation structures defined in the substrate, and a gate disposed on the substrate between adjacent isolation structures. A first doped region is defined in the substrate proximate the gate. The first doped region extends a first distance from the gate. A second doped region is defined in the substrate proximate the gate. The second doped region extends a second distance from the gate. The first distance is less than the first distance.
摘要翻译：提供一种形成半导体器件的方法。该方法包括提供其上形成有栅极的基板。在衬底中形成第一掺杂区。第一掺杂区域从栅极延伸第一距离。在衬底中形成第二掺杂区。第二掺杂区域从栅极延伸第二距离。第一距离小于第二距离。半导体器件包括衬底，限定在衬底中的隔离结构以及设置在相邻隔离结构之间的衬底上的栅极。在靠近栅极的衬底中限定第一掺杂区域。第一掺杂区域从栅极延伸第一距离。在靠近栅极的衬底中限定第二掺杂区域。第二掺杂区域从栅极延伸第二距离。第一距离小于第一距离。

4. 发明授权

US6060345A Method of making NMOS and PMOS devices with reduced masking steps 失效
标题翻译：制造具有减少掩蔽步骤的NMOS和PMOS器件的方法
公开(公告)号：US6060345A
公开(公告)日：2000-05-09
申请号：US844924
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814
摘要： A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.
摘要翻译：公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一和第二有源区上形成栅极材料，在栅极材料上形成第一掩模层，栅极材料，使用第一掩模层作为蚀刻掩模，以在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中作为注入掩模，形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层，以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中。有利地，第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂，从而在第一有源区域中提供第二导电类型的源极和漏极区域，并且在第二有源区域中提供第一导电类型的源极和漏极区域具有单个掩蔽步骤，并且不对任一个栅极施加第一和第二导电类型的掺杂剂。

5. 发明授权

US5962894A Trench transistor with metal spacers 失效
标题翻译：沟槽晶体管与金属间隔
公开(公告)号：US5962894A
公开(公告)日：1999-10-05
申请号：US30052
申请日：1998-02-24
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L29/76 , H01L31/062
CPC分类号： H01L29/41775 , H01L29/66621 , H01L29/78
摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
摘要翻译：公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体，覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

6. 发明授权

US5930634A Method of making an IGFET with a multilevel gate 失效
标题翻译：制造具有多级门的IGFET的方法
公开(公告)号：US5930634A
公开(公告)日：1999-07-27
申请号：US844927
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66575 , H01L21/28035 , H01L21/28052 , H01L29/42376 , H01L29/4925 , H01L29/6659 , H01L29/7833
摘要： A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.
摘要翻译：公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料，形成第一光致抗蚀剂层第一栅极材料，用第一图案图案照射第一光致抗蚀剂层，并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口，使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模，去除第一光致抗蚀剂层，在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平，并在其中形成源极和漏极活跃区域。有利地，第一光致抗蚀剂层可以是超薄的，以提高复制图像图案的精度，从而减少通道长度和器件性能的变化。

7. 发明授权

US5894168A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳多晶硅互连布局的集成电路的掩模生成技术，用于实现全局平坦化
公开(公告)号：US5894168A
公开(公告)日：1999-04-13
申请号：US947521
申请日：1997-10-02
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

8. 发明授权

US5877058A Method of forming an insulated-gate field-effect transistor with metal spacers 失效
标题翻译：用金属间隔物形成绝缘栅场效应晶体管的方法
公开(公告)号：US5877058A
公开(公告)日：1999-03-02
申请号：US703272
申请日：1996-08-26
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/6659 , H01L29/6656
摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.
摘要翻译：公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。金属间隔物还可以提供低电阻漏极和源极触点。

9. 发明授权

US5850105A Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 失效
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US5850105A
公开(公告)日：1998-12-15
申请号：US822120
申请日：1997-03-21
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

10. 发明授权

US5759913A Method of formation of an air gap within a semiconductor dielectric by solvent desorption 失效
标题翻译：通过溶剂解吸形成半导体电介质内气隙的方法
公开(公告)号：US5759913A
公开(公告)日：1998-06-02
申请号：US658547
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/7682 , H01L21/76828
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.
摘要翻译：提供介电材料，其具有在互连之间的介电沉积期间形成的气隙。电介质沉积在具有特定纵横比的互连隔开的几何形状中，并且在几何形状的底部暴露于吸湿电介质。在沉积期间，电介质由于从吸湿介质的湿气渗出而沿着间隔开的互连件的侧壁被迫。在一段时间内，在间隔互连的角落处堆积积聚（或缩小）时，会产生锁孔。通过在随后的步骤中降低沉积温度，最大限度地减少了沉积，并且在钥匙孔和吸湿介质上沉积。钥匙孔覆盖导致气隙由填充电介质所包围。互连之间的空气间隙有助于降低整个电介质结构的介电常数，导致互连线对线电容的减小。

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