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21. 发明授权

US07464254B2 Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data 有权
标题翻译：将专用搜索寄存器和专用状态机寄存器与相关执行硬件集成在一起的可编程处理器设备支持快速应用规则集到数据
公开(公告)号：US07464254B2
公开(公告)日：2008-12-09
申请号：US10755188
申请日：2004-01-08
申请人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Kennedy Arora
发明人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Kennedy Arora
IPC分类号： G06F7/00
CPC分类号： G06F17/30982 , G06F7/00 , G06F17/30985
摘要： A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.
摘要翻译：公开了一种规则处理器及其使用方法。在一个实施例中，规则处理器包括通用寄存器文件，提供指令的指令定序器，耦合到通用寄存器文件的解码器，以对由指令定序器指定的一组指令进行解码;以及状态机单元，解码器，并且具有状态机寄存器，用于存储耦合到状态机寄存器的一个或多个状态机和状态机执行硬件，以响应于执行该组指令中的一个或多个并且基于来自一个指令的信息来评估一个或多个状态机或解码器和通用寄存器文件两者。

22. 发明申请

US20050012521A1 Methods and apparatuses for evaluation of regular expressions of arbitrary size 失效
标题翻译：用于评估任意大小的正则表达式的方法和装置
公开(公告)号：US20050012521A1
公开(公告)日：2005-01-20
申请号：US10755048
申请日：2004-01-08
申请人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Arora
发明人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Arora
IPC分类号： G05B19/042 , G05B19/045 , G06F7/38
CPC分类号： G06F7/00 , G06F17/30985
摘要： Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.
摘要翻译：本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。

23. 发明授权

US06611910B2 Method for processing branch operations 有权
标题翻译：处理分支操作的方法
公开(公告)号：US06611910B2
公开(公告)日：2003-08-26
申请号：US09169868
申请日：1998-10-12
申请人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent G. Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
发明人： Harshvardhan Sharangpani , Tse-Yu Yeh , Michael Paul Corwin , Millind Mittal , Kent G. Fielden , Dale Morris , Rajiv Gupta , Michael Schlansker , Mircea Poplingher
IPC分类号： G06F930
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/325 , G06F9/3844 , G06F9/3846
摘要： A branch operation is processed using a branch predict instruction and an associated branch instruction. The branch predict instruction indicates a predicted direction, a target address, and an instruction address for the associated branch instruction. When the branch predict instruction is detected, the target address is stored at an entry indicated by the associated branch instruction address and a prefetch request is triggered to the target address. The branch predict instruction may also include hint information for managing the storage and use of the branch prediction information.
摘要翻译：使用分支预测指令和相关联的分支指令来处理分支操作。分支预测指示指示相关联的分支指令的预测方向，目标地址和指令地址。当检测到分支预测指令时，目标地址被存储在由关联的分支指令地址指示的条目上，并且预取请求被触发到目标地址。分支预测指令还可以包括用于管理分支预测信息的存储和使用的提示信息。

24. 发明授权

US06378063B2 Method and apparatus for efficiently routing dependent instructions to clustered execution units 有权
标题翻译：用于有效地将依赖指令路由到集群执行单元的方法和装置
公开(公告)号：US06378063B2
公开(公告)日：2002-04-23
申请号：US09220154
申请日：1998-12-23
申请人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
发明人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.
摘要翻译：与链亲和单元和周期内依赖性分析仪组合的分散单元在微处理器中路由指令以提高微处理器性能。分散单元响应于存储在链亲和单元中的信息将指令路由到微处理器中的特定簇。循环内依赖性分析器识别到分散单元的指令组的依赖性，并且分散单元基于这些依赖性来路由组中的指令。

25. 发明授权

US06237077B1 Instruction template for efficient processing clustered branch instructions 失效
标题翻译：用于高效处理集群分支指令的指令模板
公开(公告)号：US06237077B1
公开(公告)日：2001-05-22
申请号：US08949277
申请日：1997-10-13
申请人： Harshvardhan Sharangpani , Michael Paul Corwin , Dale Morris , Kent Fielden , Tse-Yu Yeh , Hans Mulder , James Hull
发明人： Harshvardhan Sharangpani , Michael Paul Corwin , Dale Morris , Kent Fielden , Tse-Yu Yeh , Hans Mulder , James Hull
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/3853 , G06F9/3861
摘要： A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are transferred to execution units indicated by a template field that is associated with the bundle. The first branch instruction in the bundle's execution sequence that is resolved taken is determined, and retirement of subsequent instructions in the execution sequence is suppressed.
摘要翻译：提供了一种用于处理指令束中的一个或多个分支指令的方法。指令以捆绑中的执行顺序排序，分支指令在序列中最后排列。捆绑的指令被传送到与捆绑相关联的模板字段指示的执行单元。确定已解决的束的执行序列中的第一个分支指令，并且抑制执行序列中后续指令的退出。

26. 发明授权

US5740093A 128-bit register file and 128-bit floating point load and store for quadruple precision compatibility 失效
标题翻译： 128位寄存器文件和128位浮点加载和存储四倍精度兼容性
公开(公告)号：US5740093A
公开(公告)日：1998-04-14
申请号：US575912
申请日：1995-12-20
申请人： Harshvardhan Sharangpani
发明人： Harshvardhan Sharangpani
IPC分类号： G06F9/312 , G06F7/38
CPC分类号： G06F9/30043
摘要： A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0's. When values are moved to memory the reverse operation is performed.
摘要翻译：一种用于提供自适应128位加载和存储操作的技术，以支持128位四重精度格式的计算的架构扩展，其中单个加载和存储指令集可在80位和128位上进行保存和恢复操作位浮点寄存器文件。 128位加载和存储指令用于移动存储器中128位对齐的值。传输需要128位存储器边界和浮点寄存器文件之间的数据移动，用于寄存器保存和恢复操作。在一个实施例中，使用80位寄存器，在第二实施例中使用128位寄存器。相同的指令在80位和128位寄存器上运行，将给定寄存器的内容映射到存储器中的128位边界字段。加载/存储单元分配位定位，使得当使用80位寄存器时，80位移动到128位边界字段的最高位位置。剩余的位位置填满0。当值移动到存储器时，执行相反的操作。

27. 发明授权

US5729724A Adaptive 128-bit floating point load and store operations for quadruple precision compatibility 失效
标题翻译：自适应128位浮点加载和存储操作，用于四重精度兼容性
公开(公告)号：US5729724A
公开(公告)日：1998-03-17
申请号：US580035
申请日：1995-12-20
申请人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
发明人： Harshvardhan Sharangpani , Donald Alpert , Hans Mulder
IPC分类号： G06F5/00 , G06F9/302 , G06F9/312 , G06F7/00
CPC分类号： G06F9/30014 , G06F5/00 , G06F9/30036 , G06F9/30043
摘要： A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating point register files. A 128-bit load and store instructions are utilized for moving values that are 128-bit aligned in memory. The transfer entails the movement of data between a 128-bit memory boundary and a floating point register file for register save and restore operations. In one embodiment, 80-bit registers are used and in a second embodiment 128-bit registers are used. The same instructions operate on both the 80-bit and 128-bit registers to map the content of a given register into a 128-bit boundary field in memory. A load/store unit allocates the bit positioning so that when 80-bit registers are used, the 80 bits are moved into the most significant bit positions of the 128-bit boundary field. The remaining bit positions are filled with 0s. When values are moved to memory the reverse operation is performed.
摘要翻译：一种用于提供自适应128位加载和存储操作的技术，以支持128位四重精度格式的计算的架构扩展，其中单个加载和存储指令集可在80位和128位上进行保存和恢复操作位浮点寄存器文件。 128位加载和存储指令用于移动存储器中128位对齐的值。传输需要128位存储器边界和浮点寄存器文件之间的数据移动，用于寄存器保存和恢复操作。在一个实施例中，使用80位寄存器，在第二实施例中使用128位寄存器。相同的指令在80位和128位寄存器上运行，将给定寄存器的内容映射到存储器中的128位边界字段。加载/存储单元分配位定位，使得当使用80位寄存器时，80位移动到128位边界字段的最高位位置。剩余的位位置用0填充。当值移动到存储器时，执行相反的操作。

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