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1. 发明申请

US20050012521A1 Methods and apparatuses for evaluation of regular expressions of arbitrary size 失效
标题翻译：用于评估任意大小的正则表达式的方法和装置
公开(公告)号：US20050012521A1
公开(公告)日：2005-01-20
申请号：US10755048
申请日：2004-01-08
申请人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Arora
发明人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Arora
IPC分类号： G05B19/042 , G05B19/045 , G06F7/38
CPC分类号： G06F7/00 , G06F17/30985
摘要： Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.
摘要翻译：本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。

2. 发明授权

US07464254B2 Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data 有权
标题翻译：将专用搜索寄存器和专用状态机寄存器与相关执行硬件集成在一起的可编程处理器设备支持快速应用规则集到数据
公开(公告)号：US07464254B2
公开(公告)日：2008-12-09
申请号：US10755188
申请日：2004-01-08
申请人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Kennedy Arora
发明人： Harshvardhan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Kennedy Arora
IPC分类号： G06F7/00
CPC分类号： G06F17/30982 , G06F7/00 , G06F17/30985
摘要： A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.
摘要翻译：公开了一种规则处理器及其使用方法。在一个实施例中，规则处理器包括通用寄存器文件，提供指令的指令定序器，耦合到通用寄存器文件的解码器，以对由指令定序器指定的一组指令进行解码;以及状态机单元，解码器，并且具有状态机寄存器，用于存储耦合到状态机寄存器的一个或多个状态机和状态机执行硬件，以响应于执行该组指令中的一个或多个并且基于来自一个指令的信息来评估一个或多个状态机或解码器和通用寄存器文件两者。

3. 发明授权

US07085918B2 Methods and apparatuses for evaluation of regular expressions of arbitrary size 失效
标题翻译：用于评估任意大小的正则表达式的方法和装置
公开(公告)号：US07085918B2
公开(公告)日：2006-08-01
申请号：US10755048
申请日：2004-01-08
申请人： Harshvardan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Kennedy Arora
发明人： Harshvardan Sharangpani , Manoj Khare , Kent Fielden , Rajesh Patil , Judge Kennedy Arora
IPC分类号： G06F15/00 , G06F17/28
CPC分类号： G06F7/00 , G06F17/30985
摘要： Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.
摘要翻译：本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。

4. 发明申请

US20070204111A1 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
公开(公告)号：US20070204111A1
公开(公告)日：2007-08-30
申请号：US11790989
申请日：2007-04-30
申请人： Manoj Khare , Faye Briggs , Akhilesh Kumar , Lily Looi , Kai Cheng
发明人： Manoj Khare , Faye Briggs , Akhilesh Kumar , Lily Looi , Kai Cheng
IPC分类号： G06F13/28
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.

5. 发明授权

US07234029B2 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 有权
标题翻译：用于减少高速缓存一致多节点架构中的存储器延迟的方法和装置
公开(公告)号：US07234029B2
公开(公告)日：2007-06-19
申请号：US09749660
申请日：2000-12-28
申请人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
发明人： Manoj Khare , Faye A. Briggs , Akhilesh Kumar , Lily P. Looi , Kai Cheng
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0862 , G06F2212/2542 , G06F2212/507
摘要： A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
摘要翻译：一种用于减少多节点架构中的存储器延迟的方法。在一个实施例中，在确定高速缓存一致性协议的结果之前，向家庭节点发出推测性读请求。家庭节点启动对存储器的读取以完成推测性读取请求。高速缓存一致性协议的结果可以由相干代理确定，以在发布推测读请求之后解析高速缓存一致性。

6. 发明授权

US06842830B2 Mechanism for handling explicit writeback in a cache coherent multi-node architecture 有权
标题翻译：在缓存一致多节点架构中处理显式回写的机制
公开(公告)号：US06842830B2
公开(公告)日：2005-01-11
申请号：US09823791
申请日：2001-03-31
申请人： Manoj Khare , Lily P. Looi , Akhilesh Kumar
发明人： Manoj Khare , Lily P. Looi , Akhilesh Kumar
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0828
摘要： A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.
摘要翻译：描述了一种用于在高速缓存相关多节点架构中处理显式回写的机制的方法和装置。在一个实施例中，本发明是一种方法。该方法包括在相干存储器系统中接收与第一行数据有关的读取请求。该方法还包括在接收到读取请求的同时接收与第一行数据相关的写入请求。该方法还包括检测读请求和写请求都与第一行相关。该方法还包括确定读和写请求的哪个请求应首先进行。此外，该方法包括完成应该首先进行的读取和写入请求的请求。

7. 发明授权

US06826619B1 Method and apparatus for preventing starvation in a multi-node architecture 失效
标题翻译：用于防止多节点架构中的饥饿的方法和装置
公开(公告)号：US06826619B1
公开(公告)日：2004-11-30
申请号：US09641708
申请日：2000-08-21
申请人： Manoj Khare , Akhilesh Kumar , Sin Sim Tan
发明人： Manoj Khare , Akhilesh Kumar , Sin Sim Tan
IPC分类号： G06F1516
CPC分类号： G06F15/17381
摘要： A method of sending messages from a node to a receiving agent. In one embodiment, if a outbound message that is stored in a buffer in the node is unsuccessfully sent to the receiving agent more than a threshold number of times, outbound messages currently stored in the buffer are sent to the receiving agent. It is determined that these outbound messages have been successfully sent before any other outbound messages are sent to the receiving agent. In a further embodiment, an outbound message is successfully sent if a success confirmation message is received for the outbound message from the receiving agent. In a still further embodiment, a retry response is received from the receiving agent for an outbound message if a buffer in the receiving agent that stores incoming outbound messages does not have room for the outbound message.
摘要翻译：从节点向接收代理发送消息的方法。在一个实施例中，如果存储在节点中的缓冲器中的出站消息不成功地发送到接收代理超过阈值次数，则当前存储在缓冲器中的出站消息被发送到接收代理。在将任何其他出站邮件发送到接收代理之前，确定这些出站邮件已成功发送。在另一实施例中，如果从接收代理接收到出站消息的成功确认消息，则成功发送出站消息。在另一个实施例中，如果接收代理中存储传入出站消息的缓冲区没有出站消息的空间，则从接收代理接收出站消息的重试响应。

8. 发明授权

US06772298B2 Method and apparatus for invalidating a cache line without data return in a multi-node architecture 有权
标题翻译：在多节点体系结构中无数据返回使高速缓存行无效的方法和装置
公开(公告)号：US06772298B2
公开(公告)日：2004-08-03
申请号：US09739667
申请日：2000-12-20
申请人： Manoj Khare , Akhilesh Kumar , Ken Creta , Lily P. Looi , Robert T. George , Michel Cekleov
发明人： Manoj Khare , Akhilesh Kumar , Ken Creta , Lily P. Looi , Robert T. George , Michel Cekleov
IPC分类号： G06F1200
CPC分类号： G06F12/0808 , G06F12/0817
摘要： A method of invalidating a cache line in a system having a plurality of nodes that include a processor and a cache memory. A request to invalidate a cache line that is caching a particular memory block is sent from a first node. The request is a request to invalidate a cache line in another node without returning to the first node the data stored in a cache line to be invalidated. In an embodiment, the data in the cache line to be invalidated is not returned to the first node even if the cache line is in the modified state. In a further embodiment, new data is written to a cache line in the first node that is caching the particular memory block without writing old data that was stored in that cache line back to a memory.
摘要翻译：一种使具有包括处理器和高速缓冲存储器的多个节点的系统中的高速缓存行无效的方法。从第一个节点发送请求使缓存特定内存块的缓存行无效。请求是使另一个节点中的高速缓存行无效的请求，而不将第一个节点的数据存储在高速缓存行中将被无效。在一个实施例中，即使高速缓存行处于修改状态，也将无效的高速缓存行中的数据返回到第一节点。在另一实施例中，将新数据写入缓存特定存储器块的第一节点中的高速缓存行，而不将存储在该高速缓存行中的旧数据写回存储器。

9. 发明授权

US06487643B1 Method and apparatus for preventing starvation in a multi-node architecture 有权
标题翻译：用于防止多节点架构中的饥饿的方法和装置
公开(公告)号：US06487643B1
公开(公告)日：2002-11-26
申请号：US09672454
申请日：2000-09-29
申请人： Manoj Khare , Akhilesh Kumar
发明人： Manoj Khare , Akhilesh Kumar
IPC分类号： G06F1200
CPC分类号： G06F12/0815 , G06F12/0813
摘要： A method of managing requests in a multi-node system. A first request associated with a location in a memory address space is sent to a first node. A second request associated with the same location in the same location in the memory address space is received before a response is received from the first node to the first request. If the received second request had been received from the first node, a retry message is sent to the first node requesting resending of the second request.
摘要翻译：一种在多节点系统中管理请求的方法。与存储器地址空间中的位置相关联的第一请求被发送到第一节点。在从第一节点接收到第一请求的响应之前，接收与存储器地址空间中的相同位置相同位置的第二请求。如果从第一节点接收到接收到的第二请求，则向第一节点发送重试消息，请求重新发送第二请求。

10. 发明申请

US20060106993A1 Mechanism for handling explicit writeback in a cache coherent multi-node architecture 审中-公开
公开(公告)号：US20060106993A1
公开(公告)日：2006-05-18
申请号：US11321632
申请日：2005-12-28
申请人： Manoj Khare , Lily Looi , Akhilesh Kumar
发明人： Manoj Khare , Lily Looi , Akhilesh Kumar
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0828
摘要： A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further includes receiving a write request relating to the first line of data at about the same time as the read request is received. The method further includes detecting that the read request and the write request both relate to the first line. The method also includes determining which request of the read and write request should proceed first. Additionally, the method includes completing the request of the read and write request which should proceed first.

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