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1. 发明授权

US06550001B1 Method and implementation of statistical detection of read after write and write after write hazards 有权
标题翻译：编写后写入和写入后的统计检测方法与实现
公开(公告)号：US06550001B1
公开(公告)日：2003-04-15
申请号：US09183156
申请日：1998-10-30
申请人： Michael P. Corwin , Dale Calvin Morris
发明人： Michael P. Corwin , Dale Calvin Morris
IPC分类号： G06F930
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3855
摘要： An apparatus is provided for detecting instruction ordering dependencies. The apparatus includes a plurality of address comparators. Each comparator including a first input adapted to receive a first operand address from one of a plurality of instructions; a second input adapted to receive a second operand address from a second one of a plurality of instructions; and an output to transmit a logic signal responsive to a match between the first and second operand addresses. The address comparators receive the first operand address from a respective, different ones of the plurality of instructions; and a hardware structure to receive the match indications from the address comparators and to indicate a dependency responsive to the match indications from a first one and a second one of the address comparators. A method is provided for detecting instruction dependencies. The method includes receiving first and second pluralities of operand addresses that correspond to first and second pluralities of operands of instructions, and selecting ones of the first and second pluralities of operands. The ones of the first and second pluralities of operands have associated respective first and second register addresses. The one of the first plurality of operands is a destination operand of a first instruction. The method also includes generating a logic signal for a dependency in response to the first and second register addresses matching and the ones of the first and second pluralities of operands being operands from different instructions.
摘要翻译：提供了一种用于检测指令排序依赖性的装置。该装置包括多个地址比较器。每个比较器包括适于从多个指令之一接收第一操作数地址的第一输入; 第二输入，适于从多个指令中的第二指令接收第二操作数地址; 以及响应于第一和第二操作数地址之间的匹配而发送逻辑信号的输出。地址比较器从多个指令中的相应不同的指令接收第一操作数地址; 以及硬件结构，用于从地址比较器接收匹配指示并且指示响应于来自地址比较器中的第一个和第二个的匹配指示的依赖性。提供了一种用于检测指令依赖性的方法。该方法包括接收对应于第一和第二多个指令操作数的第一和第二多个操作数地址，以及选择第一和第二多个操作数中的一个。第一和第二多个操作数中的那些具有相应的第一和第二寄存器地址。第一组操作数中的一个是第一指令的目标操作数。该方法还包括响应于第一和第二寄存器地址匹配产生依赖性的逻辑信号，并且第一和第二多个操作数中的一个是来自不同指令的操作数。

2. 发明授权

US06438682B1 Method and apparatus for predicting loop exit branches 有权
标题翻译：用于预测环路出口分支的方法和装置
公开(公告)号：US06438682B1
公开(公告)日：2002-08-20
申请号：US09169866
申请日：1998-10-12
申请人： Dale Morris , Mircea Poplingher , Tse-Yu Yeh , Michael P. Corwin , Wenliang Chen
发明人： Dale Morris , Mircea Poplingher , Tse-Yu Yeh , Michael P. Corwin , Wenliang Chen
IPC分类号： G06F932
CPC分类号： G06F9/325
摘要： A loop branch prediction system is provided to predict a final iteration of a loop and resteer an associated fetch module to an appropriate target address. The loop prediction system includes a counter and an end of loop (EOL) module. In one mode, the counter tracks loop branches in process. When a termination condition is detected, the counter switches to a second mode to track the number of loop branches still to be issued. The EOL module compares the number of loop branches still to be issued with one or more threshold values and generates a resteer signal when a match is detected.
摘要翻译：提供循环分支预测系统以预测循环的最终迭代并将相关联的获取模块修复到适当的目标地址。环路预测系统包括计数器和结束循环（EOL）模块。在一种模式下，计数器跟踪正在进行的循环分支。当检测到终止条件时，计数器切换到第二模式以跟踪仍然发布的循环分支的数量。 EOL模块将仍然要发出的环路分支数与一个或多个阈值进行比较，并在检测到匹配时产生一个恢复信号。

3. 发明授权

US06378063B2 Method and apparatus for efficiently routing dependent instructions to clustered execution units 有权
标题翻译：用于有效地将依赖指令路由到集群执行单元的方法和装置
公开(公告)号：US06378063B2
公开(公告)日：2002-04-23
申请号：US09220154
申请日：1998-12-23
申请人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
发明人： Michael P. Corwin , Harshvardhan Sharangpani , Hans Mulder , Ken Arora
IPC分类号： G06F938
CPC分类号： G06F9/3891 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： A dispersal unit in combination with a chain affinity unit and an intra-cycle dependency analyzer routes instructions in a microprocessor in order to improve microprocessor performance. The dispersal unit routes instructions to a particular cluster in the microprocessor in response to information stored in the chain affinity unit. The intra-cycle dependency analyzer identifies dependencies in groups of instructions to the dispersal unit, and the dispersal unit routes instructions in the group based on those dependencies.
摘要翻译：与链亲和单元和周期内依赖性分析仪组合的分散单元在微处理器中路由指令以提高微处理器性能。分散单元响应于存储在链亲和单元中的信息将指令路由到微处理器中的特定簇。循环内依赖性分析器识别到分散单元的指令组的依赖性，并且分散单元基于这些依赖性来路由组中的指令。

4. 发明授权

US6092188A Processor and instruction set with predict instructions 有权
标题翻译：具有预测指令的处理器和指令集
公开(公告)号：US6092188A
公开(公告)日：2000-07-18
申请号：US348406
申请日：1999-07-07
申请人： Michael P. Corwin , Tse-Yu Yeh , Mircea Poplingher , Carl C. Scafidi
发明人： Michael P. Corwin , Tse-Yu Yeh , Mircea Poplingher , Carl C. Scafidi
IPC分类号： G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3804 , G06F9/322 , G06F9/3846
摘要： A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the processor for a branch instruction. The processor decodes a predict instruction to obtain an associated pair of addresses comprising a predicted target address and a referenced instruction address, and fetches a predicted target instruction having an instruction address matching the predicted target address when a fetched and decoded branch instruction has an instruction address matching the referenced instruction address.
摘要翻译：一种具有指令集的处理器架构，具有预测指令，所述预测指令提供静态预测信息和静态预测的目标地址给处理器用于分支指令。处理器对预测指令进行解码以获得包括预测目标地址和参考指令地址的相关联的地址对，并且当获取和解码的分支指令具有指令地址时，获取具有与预测目标地址匹配的指令地址的预测目标指令匹配引用的指令地址。

5. 发明授权

US06591359B1 Speculative renaming of data-processor registers 有权
标题翻译：将虚拟寄存器规范映射到流水线处理器中的物理寄存器
公开(公告)号：US06591359B1
公开(公告)日：2003-07-08
申请号：US09223843
申请日：1998-12-31
申请人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
发明人： David Hass , Michael P. Corwin , Luke E. Girard , Ken Arora , Harshvardhan Sharangpani , Syed Reza
IPC分类号： G06F934
CPC分类号： G06F9/3863 , G06F9/384 , G06F9/3842
摘要： A pipelined data processor has instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical registers for speculative use by the instruction at a later pipeline stage. The registers have multiple differently translated regions. Failure of speculative renaming reverts to an archive copy of renaming data.
摘要翻译：流水线数据处理器具有不同执行阶段的指令。一些指令将虚拟地址指定为具有物理地址的寄存器的文件。推测翻译器将一个流水线阶段的指令的虚拟寄存器映射到物理寄存器，以便在稍后的流水线阶段由指令进行投机使用。寄存器有多个不同的翻译区域。投机重命名失败恢复到重命名数据的归档副本。

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