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21. 发明授权

US4695943A Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization 失效
标题翻译：具有分段周期和并发利用率的多处理器共享流水线缓存
公开(公告)号：US4695943A
公开(公告)日：1987-09-22
申请号：US655473
申请日：1984-09-27
申请人： James W. Keeley , Thomas F. Joyce
发明人： James W. Keeley , Thomas F. Joyce
IPC分类号： G06F12/08 , G06F13/00 , G11C7/00
CPC分类号： G06F12/084
摘要： A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.
摘要翻译：高速缓冲存储器单元被构造成具有可由包括两个独立操作的中央处理单元（CPU）的多个源共享的两级流水线。包括在高速缓冲存储器单元内的装置用于向两个CPU分配备用时隙，这两个CPU通过流水线阶段来抵消它们的操作。这允许高速缓冲存储器单元的一个流水线阶段对一个CPU执行目录搜索，而另一个流水线级对另一个CPU执行数据缓冲器读取。每个CPU被编程为使用少于分配给它的所有时隙。因此，处理单元无冲突运行，而流水线阶段被释放以处理来自其他来源的请求，例如来自主存储器或高速缓存更新的替换数据。

22. 发明授权

US4667288A Enable/disable control checking apparatus 失效
标题翻译：启用/禁用控制检查装置
公开(公告)号：US4667288A
公开(公告)日：1987-05-19
申请号：US509898
申请日：1983-06-30
申请人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
发明人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
IPC分类号： G06F11/07 , G06F11/10 , G06F11/22 , G06F12/00 , G06F12/12 , G11C29/00
CPC分类号： G11C29/88 , G06F11/073 , G06F11/0772 , G06F11/2289 , G06F12/126 , G06F11/10 , G06F12/00 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.
摘要翻译：其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于来自目录错误检查电路的错误信号而选择性地降级高速缓存操作到被检测为没有错误的那些级别。耦合到目录错误检查装置的测试控制装置操作以响应于从中央处理单元接收的命令选择性地启用和禁用目录错误检查电路，以便能够使用高速缓存系统的高速缓存目录和其他部分的测试常用测试程序。

23. 发明申请

US20100303085A1 BRIDGE APPARATUS AND METHODS FOR COUPLING MULTIPLE NON-FIBRE CHANNEL DEVICES TO A FIBRE CHANNEL ARBITRATED LOOP 失效
标题翻译：用于将多个非光纤通道器件耦合到光纤通道仲裁环路的桥接器件和方法
公开(公告)号：US20100303085A1
公开(公告)日：2010-12-02
申请号：US12475838
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
发明人： James W. Keeley , Douglas E. Sanders , Andrew Hyonil Chong
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： G06F13/404
摘要： Apparatus and methods for an enhanced bridge device for coupling multiple non-Fibre Channel storage devices to a Fibre Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.
摘要翻译：用于将多个非光纤通道存储设备耦合到光纤通道仲裁环（FC-AL）通信介质的增强桥接设备的装置和方法。其特征和方面提供了用于处理环路端口旁路（LPB）和环路端口使能（LPE）原语序列的FC-AL增强电路，寻址到与桥耦合的存储设备相关联的任何目标仲裁环物理地址（T-ALPA）而不考虑由桥接设备处理并与与桥接设备耦合的其他存储设备相关联的其他T-ALPA的当前旁路/非旁路状态。

24. 发明申请

US20100303084A1 APPARATUS AND METHODS FOR ACCESS FAIRNESS FOR A MULTIPLE TARGET BRIDGE/ROUTER IN A FIBRE CHANNEL ARBITRATED LOOP SYSTEM 有权
标题翻译：用于光纤通道仲裁环路系统中的多个目标桥/路由器的访问方法的装置和方法
公开(公告)号：US20100303084A1
公开(公告)日：2010-12-02
申请号：US12475694
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
发明人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
IPC分类号： H04L12/56
CPC分类号： H04L12/427
摘要： Apparatus and methods improved fair access to a Fibre Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.
摘要翻译：装置和方法通过桥接装置改善了对光纤通道仲裁环（FC-AL）通信介质的公平访问。增强型桥接器件在当前打开的访问窗口中为通过桥接设备耦合到FC-AL通信介质的所有当前请求设备提供公平的访问。因此，当在开放访问窗口中存在同时请求时，环路上的所有设备无论是直接耦合还是通过桥接设备都可以确保公平地访问环路。

25. 发明授权

US5548713A On-board diagnostic testing 失效
标题翻译：车载诊断测试
公开(公告)号：US5548713A
公开(公告)日：1996-08-20
申请号：US272893
申请日：1994-07-08
申请人： Keith L. Petry , Thomas S. Hirsch , James W. Keeley
发明人： Keith L. Petry , Thomas S. Hirsch , James W. Keeley
IPC分类号： G06F11/22 , G06F11/00
CPC分类号： G06F11/2273 , G06F11/22
摘要： A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred. The phase and subphase contents of the register are used to identify the actual test which failed. This information provides an index into a test dictionary which indicates the specific component or group of components which failed.
摘要翻译：处理单元耦合到系统总线并且包括紧密耦合到本地存储器的微处理器。处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元分别存储在第一和第二分离区域中，车载诊断（OBD）程序和引导程序。 OBD例程被组织成多个类别或阶段。处理单元包括只能由微处理器访问的寄存器，在OBD程序的控制下，在每个单独的OBD程序的开始处加载多个预定值，用于识别要执行的特定阶段和次级测试。连接到寄存器的装置被直接连接以显示寄存器的内容的第一相位部分，用于指示在发生故障的测试阶段。寄存器的相位和相位内容用于识别失败的实际测试。该信息为测试字典提供索引，该索引指示失败的组件的特定组件或组。

26. 发明授权

US5471638A Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests 失效
标题翻译：总线接口状态机可独立访问内存，处理器和寄存器，用于并发处理不同类型的请求
公开(公告)号：US5471638A
公开(公告)日：1995-11-28
申请号：US263987
申请日：1994-06-22
申请人： James W. Keeley
发明人： James W. Keeley
IPC分类号： G06F13/36 , G06F15/78 , G06F3/00
CPC分类号： G06F15/78 , G06F13/36
摘要： A processor couples to a system bus and includes a high performance microprocessor which tightly couples to a local memory. The processor is organized at the interface level into a plurality of interface sections which include a corresponding number of state machines for enabling the simultaneous processing of a plurality of different types of transactions or requests under all conditions. One interface section is organized to include the system visible registers which are accessible for reading and writing by I/O commands received from the system bus. Another section processes memory commands received from the system bus while a further section processes read/write and I/O commands issued to the system bus by the processor.
摘要翻译：处理器耦合到系统总线，并且包括紧密耦合到本地存储器的高性能微处理器。处理器在接口级别被组织成多个接口部分，其包括相应数量的状态机，用于在所有条件下能够同时处理多种不同类型的事务或请求。一个接口部分被组织成包括系统可见寄存器，可通过从系统总线接收的I / O命令进行读写。另一部分处理从系统总线接收的存储器命令，而另一部分处理由处理器发出到系统总线的读/写和I / O命令。

27. 发明授权

US5341508A Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus 失效
标题翻译：处理单元具有多个同步总线，用于共享访问和调节系统总线访问同步总线
公开(公告)号：US5341508A
公开(公告)日：1994-08-23
申请号：US771289
申请日：1991-10-04
申请人： James W. Keeley , Thomas F. Joyce
发明人： James W. Keeley , Thomas F. Joyce
IPC分类号： G06F13/40 , G06F15/80 , G06F13/42 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4027 , G06F15/8015
摘要： A processing unit tightly couples to a system bus and includes a local memory which is accessible from such bus. The processing unit includes a high performance microprocessor which tightly couples to the local memory through a high speed synchronous bus shared with a plurality of synchronous state machines. A microprocessor internal bus state machine and the plurality of state machines control local bus accesses for transferring commands generated by the microprocessor and commands transferred from the system bus under the control of an external state machine for execution by a local memory state machine and the processor state machine, respectively, which also couples to the system bus.
摘要翻译：处理单元紧密地耦合到系统总线并且包括可以从这种总线访问的本地存储器。处理单元包括通过与多个同步状态机共享的高速同步总线紧密耦合到本地存储器的高性能微处理器。微处理器内部总线状态机和多个状态机控制本地总线访问以传送由微处理器产生的命令和在外部状态机的控制下从系统总线传送的命令，以便由本地存储器状态机和处理器状态执行机器，分别也耦合到系统总线。

28. 发明授权

US5491790A Power-on sequencing apparatus for initializing and testing a system processing unit 失效
标题翻译：用于初始化和测试系统处理单元的上电排序装置
公开(公告)号：US5491790A
公开(公告)日：1996-02-13
申请号：US231856
申请日：1994-04-22
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr. , Keith L. Petry , Thomas S. Hirsch
IPC分类号： G06F1/00 , G06F9/06 , G06F9/445 , G06F11/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F11/22 , G06F9/4403
摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.
摘要翻译：除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。

29. 发明授权

US5487163A Fast synchronization of asynchronous signals with a synchronous system 失效
标题翻译：异步信号与同步系统的快速同步
公开(公告)号：US5487163A
公开(公告)日：1996-01-23
申请号：US148030
申请日：1993-11-04
申请人： James W. Keeley
发明人： James W. Keeley
IPC分类号： H03K5/135 , H03K5/13 , H03K19/003
CPC分类号： H03K5/135
摘要： A method and apparatus provides fast synchronization of asynchronous signals to use by a synchronously operated device by quantizing the delay of an input clocked bistable device which receives and stores the asynchronous signal in response to a first synchronous clock pulse so that such input clocked bistable device has a metastable time period which is less than a predetermined maximum delay period. The output signal of the input clocked bistable device is connected directly to as an input to an asynchronously operated logic circuit part selected to provide a resulting output signal corresponding to the result of performing a logical operation on the output signal within a predetermined minimum time period. The resulting output signal is directly applied to the input of another synchronously operated bistable device which stores the resulting output signal in response to the next occurring synchronous clock pulse corresponding to a time period which is greater than the time of the metastable time period, minimum delay of the logic part and preset of time of such bistable device.
摘要翻译：方法和装置通过量化响应于第一同步时钟脉冲接收和存储异步信号的输入时钟双稳态器件的延迟量化同步操作器件的异步信号来提供异步信号的快速同步，使得这种输入时钟双稳态器件具有亚稳态时间段小于预定的最大延迟周期。输入时钟双稳态器件的输出信号直接连接到异步操作的逻辑电路部分的输入，该部分被选择以在预定的最小时间周期内提供与对输出信号执行逻辑运算的结果相对应的结果输出信号。所得到的输出信号被直接施加到另一个同步操作的双稳态器件的输入端，该双稳态器件存储响应于下一个发生的同步时钟脉冲的输出信号，该时钟周期大于亚稳态时间段的时间段，最小延迟的逻辑部分和这种双稳态设备的时间预设。

30. 发明授权

US5341501A Processor bus access 失效
标题翻译：处理器总线访问
公开(公告)号：US5341501A
公开(公告)日：1994-08-23
申请号：US771582
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
发明人： James W. Keeley , Richard A. Lemay , Chester M. Nibby, Jr.
IPC分类号： G06F13/368 , G06F9/46
CPC分类号： G06F13/368
摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
摘要翻译：高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。

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