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21. 发明申请

US20070058408A1 Semiconductor memory array with serial control/address bus 有权
标题翻译：具有串行控制/地址总线的半导体存储器阵列
公开(公告)号：US20070058408A1
公开(公告)日：2007-03-15
申请号：US11226447
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
发明人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译：一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。

22. 发明申请

US20090268539A1 Chip, Multi-Chip System in a Method for Performing a Refresh of a Memory Array 失效
标题翻译：用于执行存储器阵列的刷新的方法中的芯片，多芯片系统
公开(公告)号：US20090268539A1
公开(公告)日：2009-10-29
申请号：US12108383
申请日：2008-04-23
申请人： Hermann Ruckerbauer , Dominique Savignac
发明人： Hermann Ruckerbauer , Dominique Savignac
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40615
摘要： A chip includes a memory array and a refresh counter. The refresh counter is configured to receive refresh trigger signals. The refresh counter is configured or configurable to initiate a refresh of the memory array only once per i of the received refresh trigger signals where i is a number greater than 1.
摘要翻译：芯片包括存储器阵列和刷新计数器。刷新计数器被配置为接收刷新触发信号。刷新计数器被配置或配置为仅在接收到的刷新触发信号（i是大于1的数量）的情况下才开始刷新存储器阵列一次。

23. 发明授权

US07428689B2 Data memory system and method for transferring data into a data memory 有权
标题翻译：用于将数据传送到数据存储器的数据存储器系统和方法
公开(公告)号：US07428689B2
公开(公告)日：2008-09-23
申请号：US11217081
申请日：2005-08-30
申请人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
发明人： Paul Wallner , Dominique Savignac , Christian Sichert , Thomas Hein
IPC分类号： G06F11/10
CPC分类号： G06F13/4243 , G06F11/1052
摘要： A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, the protocol includes a data mask frame in which the data mask bits are replaced by ECC bits. The method is designed such that ECC and non-ECC DRAMs can be established with the same protocol and at least a similar architecture.
摘要翻译：提出了一种使用数据协议将数据传输到数据存储器中的方法。数据存储器是纠错码（ECC）存储器或非纠错码存储器。数据协议具有不同的帧。当数据被写入ECC存储器时，该协议包括数据屏蔽帧，其中数据屏蔽位被ECC位替换。该方法被设计成使得可以使用相同的协议和至少相似的架构来建立ECC和非ECC DRAM。

24. 发明授权

US08293431B2 Lithographic mask and method of forming a lithographic mask 有权
标题翻译：平版印刷掩模和形成光刻掩模的方法
公开(公告)号：US08293431B2
公开(公告)日：2012-10-23
申请号：US12761876
申请日：2010-04-16
申请人： Haiko Rolff , Carla Byloos , Christoph Noelscher , Nicolo Morgana , Roderick Koehle , Molela Moukara , Ralf Neubauer , Rainer Pforr , Dominique Savignac
发明人： Haiko Rolff , Carla Byloos , Christoph Noelscher , Nicolo Morgana , Roderick Koehle , Molela Moukara , Ralf Neubauer , Rainer Pforr , Dominique Savignac
IPC分类号： G03F1/40
CPC分类号： G03F1/40 , G03F1/26 , G03F1/30 , G03F1/32
摘要： A lithographic mask comprises a first layer including grooves, a second layer including regions, sections and a groove-like structure that encloses the sections. The first and second layers are formed so as to reduce electrical potential differences within the second layer. A method of forming a lithographic mask includes forming first and second layers to dispose the second layer over the first layer, patterning the second layer to comprise sections, a region, and a groove-like structure enclosing the sections, and forming grooves in the first layer at portions not covered by the second layer. The first and second layers are formed to reduce potential differences within the second layers during the step of forming the grooves in the first layer.
摘要翻译：平版印刷掩模包括包括凹槽的第一层，包含区域的第二层和包围区段的凹槽状结构。形成第一层和第二层以便减小第二层内的电位差。形成光刻掩模的方法包括形成第一层和第二层以将第二层设置在第一层上，将第二层图案化以包括封闭这些区段的区段，区域和沟槽状结构，以及在第一层中形成凹槽层在未被第二层覆盖的部分。形成第一层和第二层，以在形成第一层中的槽的步骤期间减小第二层内的电位差。

25. 发明申请

US20090122628A1 DEVICE WITH PRECHARGE/HOMOGENIZE CIRCUIT 有权
标题翻译：具有预充电/均质电路的器件
公开(公告)号：US20090122628A1
公开(公告)日：2009-05-14
申请号：US12122273
申请日：2008-05-16
申请人： Dominique Savignac , Helmut Schneider
发明人： Dominique Savignac , Helmut Schneider
IPC分类号： G11C7/00
CPC分类号： H01L27/10897 , G11C11/4085 , G11C11/4094 , H01L27/0207 , H01L27/105
摘要： A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger.
摘要翻译：具有预充电/均质电路的器件。一个实施例提供至少一个开关元件用作均化器，并且至少一个开关元件充当预充电器。作为均化器的开关元件的扩散区域与作为预充电器的开关元件的扩散区域分离。

26. 发明申请

US20080217655A1 INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES 失效
标题翻译：集成电路与布线控制线结构
公开(公告)号：US20080217655A1
公开(公告)日：2008-09-11
申请号：US12028474
申请日：2008-02-08
申请人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
发明人： Dirk Baumann , Dominique Savignac , Till Schloesser , Helmut Schneider
IPC分类号： H01L29/76
CPC分类号： H01L27/10891
摘要： An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.
摘要翻译：具有埋地控制线结构的集成电路。在一个实施例中，控制线被细分为多个部分，其中不存在开关晶体管的区域沿着控制线间隔设置。至少在没有开关晶体管的区域的子集中提供用于将控制电位馈送到控制线的部分中的连接。隔离线通过相对于控制线横向运行的互连而彼此连接。

27. 发明授权

US06816432B2 Integrated semiconductor circuit having transistors that are switched with different frequencies 有权
标题翻译：具有以不同频率切换的晶体管的集成半导体电路
公开(公告)号：US06816432B2
公开(公告)日：2004-11-09
申请号：US10146582
申请日：2002-05-15
申请人： Robert Feurle , Dominique Savignac
发明人： Robert Feurle , Dominique Savignac
IPC分类号： G11C800
CPC分类号： H01L27/10873 , H01L21/823462 , H01L27/10894 , H01L27/10897
摘要： It is known to adapt the dimensions of transistors, in particular a layer thickness of a local gate oxide in a manner dependent on an operating voltage. Therefore, semiconductor circuits having transistors with different operating voltages are provided with transistors having gate oxides of different thicknesses. This allows the gate oxide thickness to be influenced even more extensively. In this case, account is taken of the fact that infrequently addressed transistors, in particular memory transistors given the same gate oxide thickness, have a significantly longer lifetime than frequently switched transistors. An integrated semiconductor circuit having transistors whose gate oxide thicknesses are adapted to the switching frequency having different magnitudes, is proposed.
摘要翻译：已知以取决于工作电压的方式适应晶体管的尺寸，特别是局部栅极氧化物的层厚度。因此，具有不同工作电压的晶体管的半导体电路设置有具有不同厚度的栅极氧化物的晶体管。这允许栅极氧化物厚度更广泛地影响。在这种情况下，考虑到这样一个事实，即不常寻址的晶体管，特别是赋予相同栅极氧化物厚度的存储器晶体，具有比频率切换晶体管显着更长的寿命。提出了具有栅极氧化物厚度适应于具有不同幅度的开关频率的晶体管的集成半导体电路。

28. 发明授权

US06458631B1 Method for fabricating an integrated circuit, in particular an antifuse 有权
标题翻译：用于制造集成电路的方法，特别是反熔丝
公开(公告)号：US06458631B1
公开(公告)日：2002-10-01
申请号：US10079045
申请日：2002-02-19
申请人： Axel Brintzinger , Ulrich Frey , Jürgen Lindolf , Dominique Savignac , Stefan Dankowski , Matthias Lehr , Jochen Müller , Kamel Ayadi
发明人： Axel Brintzinger , Ulrich Frey , Jürgen Lindolf , Dominique Savignac , Stefan Dankowski , Matthias Lehr , Jochen Müller , Kamel Ayadi
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connection of the contact (11a′).
摘要翻译：本发明提供一种制造集成电路的方法，包括以下步骤：制备电路基板（1）; 在所述电路基板（1）中提供包括第一金属的金属化区域（10a）; 在所述金属化区域（10a）之上提供第一绝缘层（25）; 在所述绝缘层（25）中形成开口（13），以便露出所述金属化区域（10a）的所述表面的至少一部分; 在所得结构上沉积功能层（15'）; 以所述开口（13）填充的方式在所得结构上方沉积第二绝缘层（35）; 第二绝缘层（35）和功能层（15'）的抛光以便露出第一绝缘层（25）的表面; 在所述开口（13）内部的所述第二绝缘层（35）中形成接触（11a'），以与所述功能层（15'）接触。以及提供用于电连接触头（11a'）的互连（40a）。

29. 发明授权

US06456522B1 Integrated memory having memory cells and buffer capacitors 有权
标题翻译：具有存储单元和缓冲电容器的集成存储器
公开(公告)号：US06456522B1
公开(公告)日：2002-09-24
申请号：US09953729
申请日：2001-09-17
申请人： Robert Feurle , Dominique Savignac
发明人： Robert Feurle , Dominique Savignac
IPC分类号： G11C700
CPC分类号： H01L29/66181 , H01L27/10805 , H01L27/10861 , H01L27/10897
摘要： An integrated memory includes memory cells each having a selector transistor and a storage capacitor. In each memory cell, the storage capacitor is connected to one of a plurality of column lines through the selector transistor, and a control terminal of the selector transistor is connected to one of a plurality of row lines. Buffer capacitors are each connected to a contact to another one of the column lines. The buffer capacitors are disposed in such a way that a connection between the respective buffer capacitor and the contact is disposed parallel to another one of the row lines. As a result, a permanently high dielectric strength is ensured through the use of the buffer capacitors.
摘要翻译：集成存储器包括各自具有选择晶体管和存储电容器的存储单元。在每个存储单元中，存储电容器通过选择晶体管连接到多条列线之一，并且选择晶体管的控制端连接到多行行之一。缓冲电容器各自连接到另一个列线的触点。缓冲电容器以这样的方式设置，使得各个缓冲电容器和触点之间的连接平行于另一条行线设置。结果，通过使用缓冲电容器确保了永久的高介电强度。

30. 发明授权

US06310399B1 Semiconductor memory configuration with a bit-line twist 有权
标题翻译：半导体存储器配置有位线扭曲
公开(公告)号：US06310399B1
公开(公告)日：2001-10-30
申请号：US09514268
申请日：2000-02-28
申请人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
发明人： Robert Feurle , Sabine Mandel , Dominique Savignac , Helmut Schneider
IPC分类号： H01L2348
CPC分类号： H01L27/10885 , H01L23/5225 , H01L27/10891 , H01L27/10897 , H01L2924/0002 , Y10S257/907 , H01L2924/00
摘要： A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane. The dummy contacts lead to the word-line plane to give the word lines a homogeneous environment. The further plane can be a word-line plane including the word lines. The bit lines in the twist-free area can be approximately from 150 nm to 250 nm wide, preferably 200 nm. The twist area can only include the twist of the bit lines. The bit lines in the twist area can be approximately from 250 nm to 350 nm wide, preferably, 330 nm wide. The bit lines can have spacing from 150 to 180 nm wide. The bit lines, the word lines, the contacts, and the dummy contacts can be made from copper or aluminum.
摘要翻译：半导体存储器配置包括位线平面中的位线，不同于位线平面的另一个平面，字线和与位线平面相邻的存储单元区域，一些位线沿着一条扭转位线中的其他位线被解捻，一些位线的对成对分别限定扭转位线对，扭转位线对具有用于使扭转位线对的一个位线交叉的触点扭转位线对的另一个位线和通过另一个平面的存储单元区域之后，未扭绞的其它位线具有从位线平面引导到另一个平面的虚拟触点。虚拟触点导致字线平面，使字线成为均匀的环境。另外的平面可以是包括字线的字线平面。无捻区域中的位线可以约为150nm至250nm宽，优选为200nm。扭曲区域只能包括位线的扭曲。扭转区域中的位线可以约为250nm至350nm宽，优选为330nm宽。位线可以具有150至180nm宽的间距。位线，字线，触点和虚拟触点可以由铜或铝制成。

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