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    • 1. 发明授权
    • Method for fabricating an integrated circuit, in particular an antifuse
    • 用于制造集成电路的方法,特别是反熔丝
    • US06458631B1
    • 2002-10-01
    • US10079045
    • 2002-02-19
    • Axel BrintzingerUlrich FreyJürgen LindolfDominique SavignacStefan DankowskiMatthias LehrJochen MüllerKamel Ayadi
    • Axel BrintzingerUlrich FreyJürgen LindolfDominique SavignacStefan DankowskiMatthias LehrJochen MüllerKamel Ayadi
    • H01L2182
    • H01L23/5256H01L2924/0002H01L2924/00
    • The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate (1); providing a metallization region (10a) comprising a first metal in the circuit substrate (1); providing a first insulation layer (25) above the metallization region (10a); forming an opening (13) in the insulating layer (25) in order to uncover at least part of the surface of the metallization region (10a); depositing a functional layer (15′) above the resulting structure; depositing a second insulating layer (35) above the resulting structure, in such a manner that the opening (13) is filled; polishing-back of the second insulating layer (35) and of the functional layer (15′) in order to uncover the surface of the first insulating layer (25); forming a contact (11a′) in the second insulating layer (35) inside the opening (13) in order to make contact with the functional layer (15′); and providing an interconnect (40a) for electrical connection of the contact (11a′).
    • 本发明提供一种制造集成电路的方法,包括以下步骤:制备电路基板(1); 在所述电路基板(1)中提供包括第一金属的金属化区域(10a); 在所述金属化区域(10a)之上提供第一绝缘层(25); 在所述绝缘层(25)中形成开口(13),以便露出所述金属化区域(10a)的所述表面的至少一部分; 在所得结构上沉积功能层(15'); 以所述开口(13)填充的方式在所得结构上方沉积第二绝缘层(35); 第二绝缘层(35)和功能层(15')的抛光以便露出第一绝缘层(25)的表面; 在所述开口(13)内部的所述第二绝缘层(35)中形成接触(11a'),以与所述功能层(15')接触。 以及提供用于电连接触头(11a')的互连(40a)。
    • 2. 发明授权
    • Integrated semiconductor circuit with an electrically programmable switching element
    • 具有电可编程开关元件的集成半导体电路
    • US07126204B2
    • 2006-10-24
    • US10886017
    • 2004-07-07
    • Ulrich FreyAndreas FelberJürgen Lindolf
    • Ulrich FreyAndreas FelberJürgen Lindolf
    • H01L29/00H01L29/32H01L29/74H01L31/111H01L29/34
    • H01L23/5252H01L2924/0002H01L2924/00
    • The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) includes at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V−), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V−) together with the substrate potential (Vo). In addition, the substrate electrode (2) is shielded from the substrate potential (Vo) by a current barrier layer (7). This allows the second potential to be lowered below the substrate potential or to be raised above it; the resulting increased programming voltage does not endanger other circuit regions.
    • 本发明涉及一种具有电可编程开关元件(10)的半导体电路(20),包括基板电极(2)的“反熔丝”,该基板电极(2)在基板(1)中产生,该基板电极可被基板电位 (Vo)和通过绝缘层(8)与衬底电极(2)隔离的对置电极(5),其中衬底电极(2)包括至少一个高掺杂衬底区域(3),并且其中 对置电极(5)可以连接到可以设置在半导体电路(20)外部的外部第一电位(V +)。 根据本发明,衬底电极(2)可以连接到设置在电路内部并且与外部第一电位(V +)一起产生更高编程电压(V +)的第二电位(V-) V)与外部第一电位(V-)一起以及衬底电位(Vo)。 此外,通过电流阻挡层(7)将衬底电极(2)与衬底电位(Vo)屏蔽。 这允许将第二电位降低到低于衬底电位或在其上方升高; 所产生的增加的编程电压不会危及其他电路区域。
    • 3. 发明授权
    • Fabrication method for a semiconductor structure and corresponding semiconductor structure
    • 半导体结构的制造方法和相应的半导体结构
    • US07235447B2
    • 2007-06-26
    • US11035705
    • 2005-01-14
    • Ulrich FreyMatthias GoldbachDirk Offenberg
    • Ulrich FreyMatthias GoldbachDirk Offenberg
    • H01L21/8234
    • H01L29/4983H01L21/28247H01L21/823468H01L27/105H01L27/1052H01L29/6656
    • The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps:provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2); and selective oxidation of the uncovered bottommost layer (10) for the purpose of forming sidewall oxide regions (50′) on the gate stacks (GS1; GS2).
    • 本发明提供一种用于半导体结构和相应的半导体结构的制造方法。 制造方法包括以下步骤:提供具有栅极电介质(5)的半导体衬底(1); 提供多个多层细长的栅极叠层(GS1; GS2),其基本上在栅极电介质(5)上彼此平行地延伸,该栅极堆叠具有由硅制成的最底层(10); 提供由栅极叠层(GS1; GS2)和栅极电介质(5)制成的由第一材料制成的第一衬垫层(60)未被覆盖在其后面,衬垫层的厚度(h)小于 由硅制成的最下层(10)的厚度(h'); 在第一衬垫层(60)上设置由栅极堆叠(GS1; GS2)的垂直侧壁上的由第二材料制成的侧壁间隔物(70),第一衬里层(60)的位于栅极电介质 (5)在栅极堆栈(GS 1; GS 2)之间保持自由; 为了横向露出由栅极堆叠(GS1; GS2)的硅制成的最底层(10)的目的,相对于侧壁间隔物(70)选择性地去除第一衬里层(60) 以及为了在栅极堆叠(GS1; GS2)上形成侧壁氧化物区域(50'),未覆盖的最底层(10)的选择性氧化。
    • 5. 发明授权
    • Evaluation circuit for an anti-fuse
    • 防熔断器评估电路
    • US06549063B1
    • 2003-04-15
    • US10044470
    • 2002-01-11
    • Gunther LehmannUlrich Frey
    • Gunther LehmannUlrich Frey
    • H01H3776
    • H01L23/5256G01R31/07G11C17/18H01L2924/0002H01L2924/00
    • The present invention provides for evaluating a programmable anti-fuse element. For a programmable transistor anti-fuse, the gate of the anti-fuse is precharged with a predetermined voltage and/or current and the anti-fuse is subsequently evaluated. In one embodiment a precharge voltage sufficient to turn ON a transistor is provided to the gate. Here, an intact (unblown) transistor remains ON over a period of time and a damaged (blown) transistor dissipates the charge voltage and turns OFF. The status of the transistor is subsequently determined by evaluating the resistance between the drain and source. A high resistance indicates a blown condition and a low resistance indicates an unblown condition. In another embodiment, a small current is provided to the gate in which the small current is greater than a leakage current for an intact transistor and is less than a leakage current for a damaged transistor. An intact transistor charges to an ON state over a period of time but a damaged transistor does not because it's leakage current is greater than the small current provided to the gate. Again, the status of the transistor anti-fuse is subsequently determined by evaluating the resistance between the drain and source.
    • 本发明提供了一种可编程反熔丝元件的评估。 对于可编程晶体管反熔丝,反熔丝的栅极以预定的电压和/或电流进行预充电,并且随后评估反熔丝。 在一个实施例中,向栅极提供足以导通晶体管的预充电电压。 这里,一个完整的(未吹制的)晶体管在一段时间内保持导通,并且损坏的(熔断)晶体管消耗充电电压并且关断。 随后通过评估漏极和源极之间的电阻来确定晶体管的状态。 高电阻表示吹出状态,低电阻表示未吹出状态。 在另一个实施例中,小电流被提供给栅极,其中小电流大于完整晶体管的漏电流,并且小于损坏晶体管的漏电流。 完整的晶体管在一段时间内充电到ON状态,但损坏的晶体管不是因为其漏电流大于提供给栅极的小电流。 再次,晶体管反熔丝的状态随后通过评估漏极和源极之间的电阻来确定。
    • 7. 发明申请
    • Integrated semiconductor circuit with an electrically programmable switching element
    • 具有电可编程开关元件的集成半导体电路
    • US20050073024A1
    • 2005-04-07
    • US10886017
    • 2004-07-07
    • Ulrich FreyAndreas FelberJurgen Lindolf
    • Ulrich FreyAndreas FelberJurgen Lindolf
    • H01L23/525H01L29/00H01L23/58H01L23/62
    • H01L23/5252H01L2924/0002H01L2924/00
    • The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which comprises a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) comprises at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V−), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V−) together with the substrate potential (Vo). In addition, the substrate electrode (2) is shielded from the substrate potential (Vo) by a current barrier layer (7). This allows the second potential to be lowered below the substrate potential or to be raised above it; the resulting increased programming voltage does not endanger other circuit regions.
    • 本发明涉及一种具有电可编程开关元件(10)的半导体电路(20),“反熔丝”,其包含基板电极(2),该基板电极(2)在基板(1)中产生,该基板电极可被基板电位 (Vo)和通过绝缘层(8)与衬底电极(2)隔离的对置电极(5),其中衬底电极(2)包括至少一个高掺杂衬底区域(3),并且其中 对置电极(5)可以连接到可以设置在半导体电路(20)外部的外部第一电位(V +)。 根据本发明,衬底电极(2)可以连接到设置在电路内部并且与外部第一电位(V +)一起产生更高编程电压(V +)的第二电位(V-) V)与外部第一电位(V-)一起以及衬底电位(Vo)。 此外,通过电流阻挡层(7)将衬底电极(2)与衬底电位(Vo)屏蔽。 这允许将第二电位降低到低于衬底电位或在其上方升高; 所产生的增加的编程电压不会危及其他电路区域。